Abstract: This document describes techniques for performing track associations at least partially based on low confidence detections. For object trackers, which rely on measurement detections that are associated with a reported confidence, there is no direct tradeoff between a true positive track rate and a false positive track rate that applies to improving the accuracy of state estimates of tracks. To increase the true positive track rate while reducing the false positive track rate, a parameter is maintained for each track. Referred to as Probability of Existence (PoE), it is an estimate of likelihood that a real object exists with a true state that approximates an estimated state for that track. By considering PoE in combination with the reported confidence in the measurement detections being used, object tracking using radar and other sensors technologies is improved, so real-objects are reported more-quickly and accurately, and false objects are reported less often.

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

Abstract: Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.

Abstract: A modular noseroller assembly for transitioning a conveyor belt at an end of a carryway comprises a plurality of roller-mounting modules connected to a spacer element to form a noseroller assembly that can be installed in a conveyor frame. The roller-mounting modules mount freely-rotating rollers on an axle extending through the plurality of roller-mounting modules. The configuration and size of the noseroller assembly can be easily modified depending on a particular application.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to defer performance of an error-correction parity calculation for a block of a memory components of the memory subsystem. In particular, a memory sub-system controller of some embodiments can defer (e.g., delay) performance of an error-correction parity calculation and can defer the error-correction parity calculation such that it is performed at a time when the memory sub-system satisfies an idle state condition.

Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.

Abstract: The present invention relates to IoT devices existing in a deployed ecosystem. The various computers in the deployed ecosystem are able to respond to requests from a device directly associated with it in a particular hierarchy, or it may seek a response to the request from a high order logic/data source (parent). The logic/data source parent may then repeat the understanding process to either provide the necessary response to the logic/data source child who then replies to the device or it will again ask a parent logic/data sources for the appropriate response. This architecture allows for a single device to make one request to a single known source and potentially get a response back from the entire ecosystem of distributed servers.

Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: The present invention relates to IoT devices existing in a deployed ecosystem. The various computers in the deployed ecosystem are able to respond to requests from a device directly associated with it in a particular hierarchy, or it may seek a response to the request from a high order logic/data source (parent). The logic/data source parent may then repeat the understanding process to either provide the necessary response to the logic/data source child who then replies to the device or it will again ask a parent logic/data sources for the appropriate response. This architecture allows for a single device to make one request to a single known source and potentially get a response back from the entire ecosystem of distributed servers.

Abstract: Devices and techniques are disclosed herein for predicting and optimizing energy usage of a device during low-power operation. In an example, a method can include storing a duration of a plurality of low-power intervals of a device, determining a probable duration of a next low-power interval of the device based on the durations of the plurality of low-power intervals, determining a low-power state of the device for the next low-power interval based on the probable duration, upon initiating the next low-power interval, saving state information of one or more sub-systems of the device to provide first state information in response to the low-power state, and upon initiating the next low-power interval, reducing a power state of the one or more sub-systems.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: Wire-based metallization and stringing techniques for solar cells, and the resulting solar cells, modules, and equipment, are described. In an example, a substrate has a surface. A plurality of N-type and P-type semiconductor regions is disposed in or above the surface of the substrate. A conductive contact structure is disposed on the plurality of N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of conductive wires, each conductive wire of the plurality of conductive wires essentially continuously bonded directly to a corresponding one of the N-type and P-type semiconductor regions.

Abstract: A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a first emitter region over a substrate, the first emitter region having a perimeter around a portion of the substrate. A first conductive contact is electrically coupled to the first emitter region at a location outside of the perimeter of the first emitter region.

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

Abstract: The present invention relates to IoT devices existing in a deployed ecosystem. The various computers in the deployed ecosystem are able to respond to requests from a device directly associated with it in a particular hierarchy, or it may seek a response to the request from a high order logic/data source (parent). The logic/data source parent may then repeat the understanding process to either provide the necessary response to the logic/data source child who then replies to the device or it will again ask a parent logic/data sources for the appropriate response. This architecture allows for a single device to make one request to a single known source and potentially get a response back from the entire ecosystem of distributed servers.

Abstract: Metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, solar cell circuit, solar cell strings, and solar cell arrays are described. A solar cell string can include a plurality of solar cells. The plurality of solar cells can include a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding one of the semiconductor regions.

Abstract: A method is provided for performing dynamic inferencing at a node configured to communicate with other nodes of an IoT hierarchy. In the method, a schema for an asset object associated with one or more of at least one physical process and at least one physical device is received at the node. The schema is formatted according to an inferencing engine model format. An artificial intelligence model capable of being executed in an inferencing engine is received at the node. Data indicative of one or more of a current state of at least one physical process and a current state of at least one physical device is received at the node. The received data according to the schema and an inferencing engine are processed at the node. The inferencing engine generates a new predictive attribute based on the set of attributes, and the processing normalizes the received data according to the schema to generate normalized data, the normalized data includes the predictive attribute from the inferencing engine.

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a flash storage system. In an example, read commands or write commands can optionally include a file-type indicator. The file-type indicator can allow for exchange of data between the host and the flash storage system using a single record of a Flash Translation Layer (FTL) table or logical-to-physical (L2P) table, and where the amount of data can be much larger than the atomic unit associated with the flash storage system.

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.