Patents by Inventor David Aaron

David Aaron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CACHE BLOCK BUDGETING TECHNIQUES
    Publication number: 20230236986
    Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 27, 2023
    Inventors: Deping He, David Aaron Palmer
  • HOST-CONFIGURABLE ERROR PROTECTION
    Publication number: 20230214294
    Abstract: Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 6, 2023
    Inventors: David Aaron Palmer, Jonathan S. Parry
  • POWER CONTROL FOR BOOT-UP OF MEMORY SYSTEMS
    Publication number: 20230214137
    Abstract: Methods, systems, and devices for power control for boot-up of memory systems are described. A memory system may be configured to boot-up using two different power modes: a lower-power mode, and a higher-power mode. The memory system may perform a series of evaluations to determine whether the memory system is to switch to the lower-power mode during boot-up operations, or stay in the higher-power mode. For example, the memory system may check one or more of: a history of previous boot-up failures, a voltage of an associated power management integrated circuit, a history of asynchronous power loss at the device, a power-mode configuration of the host device, or a history of host-initiated power-down commands. In some examples, by switching to the lower-power mode, the memory system may avoid repeatedly failing multiple boot-up cycles and may instead successfully boot-up the memory system.
    Type: Application
    Filed: May 4, 2022
    Publication date: July 6, 2023
    Inventors: David Aaron Palmer, Jonathan S. Parry
  • Garbage collection adapted to memory device life expectancy
    Patent number: 11693769
    Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Deping He, David Aaron Palmer
  • Cryptographic data integrity protection
    Patent number: 11693732
    Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Nadav Grosz, Lance W. Dover, Yoav Weinberg
  • AUTOMATED SAMPLE HANDLING INSTRUMENTATION, SYSTEMS, PROCESSES, AND METHODS
    Publication number: 20230204616
    Abstract: A sample processing station includes two or more container holders on a platform that is rotatable about a central axis of rotation. Each holder is configured to rotate about a secondary axis of rotation. The station includes a capping/decapping mechanism to cap or decap a container held in one of the container holders and an elevator with a chuck guide that contact the container holder as the chuck is lowered by the elevator to positon the chuck with respect to the cap of the container held in the holder and to hold jaws of the container holder in a closed position. In embodiment, the chuck guide includes a yoke with opposed arms and spindles located near distal ends of the arms that engage beveled shoulders of the container holder.
    Type: Application
    Filed: February 20, 2023
    Publication date: June 29, 2023
    Applicant: Gen-Probe Incorporated
    Inventors: Rolf SILBERT, David Opalsky, David Aaron Buse, Robert J. Rosati, Olev Tammer, Richard Capella, Matthias Merten
  • Arbitration techniques for managed memory
    Patent number: 11687277
    Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include initiating a first plurality of host-requested NAND memory operations of a first type at a first channel of a memory device for a first interval, and, at the completion of the first interval, performing a second plurality of homogeneous, host-requested NAND memory operations of a second type at the first multiple plane memory die for a second interval.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Host-resident translation layer validity check techniques
    Patent number: 11687469
    Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Laser assisted metallization process for solar cell fabrication
    Patent number: 11682737
    Abstract: A method for fabricating a solar cell and the and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. The method can include: providing a solar cell having metal foil having first regions that are electrically connected to semiconductor regions on a substrate at a plurality of conductive contact structures, and second regions; locating a carrier sheet over the second regions; bonding the carrier sheet to the second regions; and removing the carrier sheet from the substrate to selectively remove the second regions of the metal foil.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: June 20, 2023
    Assignee: Maxeon Solar Pte. Ltd.
    Inventors: Pei Hsuan Lu, Benjamin I. Hsia, David Aaron Randolph Barkhouse, Lewis C. Abra, George G. Correos, Boris Bastien
  • Host inquiry response generation in a memory device
    Patent number: 11681461
    Abstract: Devices and techniques for generating a response to a host with a memory device are provided. A first command from a host can be executed. A status for the first command can he determined. An inquiry from the host about a second command can be received after execution of the first command has begun. A response can be made to the inquiry that includes information about the second command and the status for the first command.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: June 20, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Nadav Grosz, David Aaron Palmer
  • Edge synchronization systems and methods
    Patent number: 11683110
    Abstract: The present invention relates to IoT devices existing in a deployed ecosystem. The various computers in the deployed ecosystem are able to respond to requests from a device directly associated with it in a particular hierarchy, or it may seek a response to the request from a high order logic/data source (parent). The logic/data source parent may then repeat the understanding process to either provide the necessary response to the logic/data source child who then replies to the device or it will again ask a parent logic/data sources for the appropriate response. This architecture allows for a single device to make one request to a single known source and potentially get a response back from the entire ecosystem of distributed servers.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 20, 2023
    Assignee: Clearblade, Inc.
    Inventors: David Aaron Allsbrook, Steven Manweiler, Sanket Deshpande, Martin Pandola
  • DYNAMIC LOGICAL PAGE SIZES FOR MEMORY DEVICES
    Publication number: 20230185727
    Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 15, 2023
    Inventors: Sharath Chandra Ambula, David Aaron Palmer, Venkata Kiran Kumar Matturi, Sri Ramya Pinisetty, Sushil Kumar
  • VALID DATA IDENTIFICATION FOR GARBAGE COLLECTION
    Publication number: 20230185713
    Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.
    Type: Application
    Filed: October 18, 2022
    Publication date: June 15, 2023
    Inventor: David Aaron Palmer
  • METHODS AND SYSTEMS FOR MIXING FLUIDS
    Publication number: 20230184428
    Abstract: A mixing chamber is loaded with a first fluid. While a volume of the first fluid within the mixing chamber is constant, first and second streams of a second fluid are injected into the mixing chamber along first and second injection directions. As a result of injecting the first and second streams of the second fluid into the mixing chamber, the first and second streams of the second fluid impinge one another so as to generate within the mixing chamber at least one further stream of the second fluid that mixes with the first fluid and that flows in a direction different to the first and second injection directions.
    Type: Application
    Filed: November 28, 2022
    Publication date: June 15, 2023
    Inventors: Tim Coleman, Kenneth William Kratschmar, David Aaron Leboe, Christopher Edwin John Reid
  • Asset synchronization systems and methods
    Patent number: 11671490
    Abstract: The present invention relates to IoT devices existing in a deployed ecosystem. The various computers in the deployed ecosystem are able to respond to requests from a device directly associated with it in a particular hierarchy, or it may seek a response to the request from a high order logic/data source (parent). The logic/data source parent may then repeat the understanding process to either provide the necessary response to the logic/data source child who then replies to the device or it will again ask a parent logic/data sources for the appropriate response. This architecture allows for a single device to make one request to a single known source and potentially get a response back from the entire ecosystem of distributed servers.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 6, 2023
    Assignee: Clearblade, Inc.
    Inventors: David Aaron Allsbrook, Steven Manweiler, Sanket Deshpande, Martin Pandola
  • Laser assisted metallization process for solar cell stringing
    Patent number: 11664472
    Abstract: Metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, solar cell circuit, solar cell strings, and solar cell arrays are described. A solar cell string can include a plurality of solar cells. The plurality of solar cells can include a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding one of the semiconductor regions.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: May 30, 2023
    Assignee: Maxeon Solar Pte. Ltd.
    Inventors: Pei Hsuan Lu, Benjamin I. Hsia, David Aaron Randolph Barkhouse, Lewis C. Abra, George G. Correos, Marc Robinson, Paul W. Loscutoff, Ryan Reagan, David Okawa, Tamir Lance, Thierry Nguyen
  • Managing reduced power memory operations
    Patent number: 11656673
    Abstract: A memory device includes a hardware suspend mechanism configured to place a component of a memory controller into a lower power mode while a memory operation is being completed. A timer is provided to wakeup the CPU out of the lower power mode; and hardware interrupts can be used in determining to either enter or wake from the lower power mode. Memory monitoring circuitry is provided to estimate the duration of memory operations; and timers are provided to wake the component in the absence of hardware interrupts or additional commands.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Jonathan Scott Parry, David Aaron Palmer, Stephen Hanna
  • Filter diffuser
    Patent number: 11654859
    Abstract: A diffuser includes a first tube and a second tube. The first tube includes a key and defines a first opening. The second tube is inserted through the first opening. The second tube defines a notch. The key is inserted into the notch.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 23, 2023
    Assignee: Illinois Tool Works Inc.
    Inventors: Randall Joseph Schoenborn, John David Bisset, David Aaron Prymula
  • Host timeout avoidance in a memory device
    Patent number: 11656794
    Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A tinier of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Nadav Grosz, David Aaron Palmer
  • Method for receiving a request for an API in an IoT hierarchy
    Patent number: 11652741
    Abstract: The present invention relates to IoT devices existing in a deployed ecosystem. The various computers in the deployed ecosystem are able to respond to requests from a device directly associated with it in a particular hierarchy, or it may seek a response to the request from a high order logic/data source (parent). The logic/data source parent may then repeat the understanding process to either provide the necessary response to the logic/data source child who then replies to the device or it will again ask a parent logic/data sources for the appropriate response. This architecture allows for a single device to make one request to a single known source and potentially get a response back from the entire ecosystem of distributed servers.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 16, 2023
    Assignee: Clearblade, Inc.
    Inventors: David Aaron Allsbrook, Steven Manweiler, Sanket Deshpande, Martin Pandola