Patents by Inventor David G. Figueroa
David G. Figueroa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8166215Abstract: Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.Type: GrantFiled: December 28, 2005Date of Patent: April 24, 2012Assignee: Intel CorporationInventors: Srikrishnan Venkataraman, Jayashree Kar, Sudarshan D. Solanki, Priyavadan Ramdas Patel, Michael M. DeSmith, David G. Figueroa
-
Patent number: 7975158Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 31, 2007Date of Patent: July 5, 2011Assignee: Intel CorporationInventors: Muhammed Elgousi, Jayashree Kar, David G. Figueroa, Srikrishnan Venkataraman
-
Publication number: 20090259787Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 31, 2007Publication date: October 15, 2009Inventors: Muhammed Elgousi, Jayashree Kar, David G. Figueroa, Srikrishnan Venkataraman
-
Patent number: 7535728Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: August 22, 2006Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
-
Patent number: 7518248Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.Type: GrantFiled: August 4, 2006Date of Patent: April 14, 2009Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa
-
Patent number: 7492605Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.Type: GrantFiled: June 22, 2006Date of Patent: February 17, 2009Assignee: Intel CorporationInventors: Yuan-Liang Li, Jayashree Kar, David G. Figueroa, Dong Zhong
-
Patent number: 7417872Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.Type: GrantFiled: July 26, 2006Date of Patent: August 26, 2008Assignee: Intel CorporationInventors: Yuan-Liang Li, Jiangqi He, Dong Zhong, David G. Figueroa
-
Patent number: 7358607Abstract: Arrangements are used for minimizing signal path discontinuities.Type: GrantFiled: March 6, 2002Date of Patent: April 15, 2008Assignee: Intel CorporationInventors: David G. Figueroa, Yuan-Liang Li
-
Publication number: 20070295818Abstract: A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.Type: ApplicationFiled: June 22, 2006Publication date: December 27, 2007Inventors: Yuan-Liang Li, Jayashree Kar, David G. Figueroa, Dong Zhong
-
Patent number: 7286368Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.Type: GrantFiled: October 29, 2004Date of Patent: October 23, 2007Assignee: Intel CorporationInventors: Dong Zhong, David G. Figueroa, Yuan-Liang Li, Michael M. Desmith
-
Patent number: 7221046Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts, and an element having a plurality of resistive portions, each of the plurality of resistive portions being coupled to a respective one of the plurality of conductive contacts. The integrated circuit package may further include a decoupling capacitor having a plurality of capacitor pads, each of the plurality of capacitor pads being coupled to a respective one of the plurality of resistive portions.Type: GrantFiled: October 21, 2004Date of Patent: May 22, 2007Assignee: Intel CorporationInventors: Dong Zhong, David G. Figueroa, Yuan-Liang Li
-
Patent number: 7215530Abstract: In some embodiments, a capacitor includes a first conductive layer electrically coupled to a first terminal, a second conductive layer electrically coupled to a second terminal, a floated conductive layer disposed between the first and second conductive layers, and a plurality of non-conductive layers respectively disposed between each of the conductive layers. Other embodiments are disclosed and claimed.Type: GrantFiled: June 30, 2005Date of Patent: May 8, 2007Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa, Nicholas L. Holmberg
-
Patent number: 7212395Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.Type: GrantFiled: December 28, 2004Date of Patent: May 1, 2007Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa, Farzaneh Yahyaei-moayyed, Dong Zhong
-
Patent number: 7211894Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.Type: GrantFiled: April 12, 2005Date of Patent: May 1, 2007Assignee: Intel CorporationInventors: Jennifer A. Hester, Yuan-Liang Li, Michael M. Desmith, David G. Figueroa, Dong Zhong
-
Patent number: 7176565Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.Type: GrantFiled: December 3, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa, Chee-Yee Chung
-
Patent number: 7145239Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.Type: GrantFiled: October 29, 2004Date of Patent: December 5, 2006Assignee: Intel CorporationInventors: Yuan-Liang Li, Jiangqi He, Dong Zhong, David G. Figueroa
-
Patent number: 7133294Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.Type: GrantFiled: March 15, 2005Date of Patent: November 7, 2006Assignee: Intel CorporationInventors: Priyavadan R. Patel, Chee-Yee Chung, David G. Figueroa, Robert L. Sankman, Yuan-Liang Li, Hong Xie, William P. Pinello
-
Patent number: 7120031Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: July 2, 2004Date of Patent: October 10, 2006Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
-
Patent number: 7111271Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.Type: GrantFiled: October 28, 2002Date of Patent: September 19, 2006Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa
-
Patent number: 7063569Abstract: A socket and fabrication method provide enhanced performance. The socket includes a base, and a plurality of signal contacts disposed within the base. A grounding fence is also disposed within the base such that the grounding fence laterally isolates the signal contacts from one another. The use of a grounding fence therefore enables elimination or significant reduction of ground contacts and therefore provides more signaling opportunities for a given amount of real estate.Type: GrantFiled: November 12, 2003Date of Patent: June 20, 2006Assignee: Intel CorporationInventors: David G. Figueroa, Yuan-Liang Li