Abstract: In one embodiment of the invention, an integral capacitor includes a power plane, a ground plane, and a dielectric layer. The power plane has a power surface and a power periphery. The power plane couples power to signals of an integrated circuit operating at a fundamental frequency. The first ground plane have a first ground surface and a first ground periphery. The first ground plane couples ground to the signals. The first ground plane is separated from the power plane by a first distance. The first ground surface is larger than the power surface and the first ground periphery extends at least a second distance from the power periphery. The second distance is at least larger than N times the first distance. The dielectric layer is formed between the power plane and the first ground plane.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.

Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.

Abstract: A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

Abstract: The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.

Abstract: An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.

Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7B). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber.

Abstract: An apparatus includes a socket and a housing. The socket and the housing can define an interior region for receiving an integrated circuit package. The housing includes a conductive member with a first portion exposed adjacent a bottom surface of the housing and a second portion at a side surface adjacent the interior region. The first portion can be electrically in contact with a printed circuit board. The second portion can be electrically in contact with a conductive member at a side surface of the integrated circuit package.

Abstract: A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer.

Abstract: An integrated circuit socket includes one or more cavities formed in a top surface of the socket, where the one or more cavities are formed in a region over which an integrated circuit can be placed. Multiple conductive contacts are attached to the socket, where each contact includes a first member that extends into one of the cavities, and a second member that provides at least part of a conductive path between the first member and the socket. The first member at least partially holds in place a discrete device inserted into the cavity. An integrated circuit package or interposer attached to the top surface over the cavity also can at least partially hold the discrete device in place. The first member makes electrical contact with the discrete device, thus completing a conductive path between the discrete device and the integrated circuit.

Abstract: A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer.

Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber.

Abstract: An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.

Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material.

Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber.

Abstract: A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).

Abstract: An electronic circuit package (400, FIG. 4) includes one or more trench vias (404, FIG. 4). Each trench via makes electrical contact with one or more terminals (526, FIG. 5) of a discrete device (520, FIG. 5) embedded within the package. A trench via can extend to a surface of the package, or one or more conventional vias (620, FIG. 6) formed within layers (602, FIG. 6) above or below the trench via can electrically connect the trench via, and thus the discrete device, to the surface of the package. The discrete device (520, FIG. 5) can be a capacitor, in one embodiment, providing decoupling capacitance to an integrated circuit load. Besides being implemented in a package, the trench vias also could be implemented in other types of electronic circuit housings (e.g., interposers, sockets, and printed circuit boards).

Abstract: The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.