Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on nonconductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract: An integrated circuit socket with capacitors and shunts is disclosed. According to one embodiment of the invention, a socket is divided into a shunt area, a socket pin area, and a land side capacitor area. The shunt area may contain a variable number of power shunts, ground shunts, and capacitors. The capacitors are connected across, and serve to decouple, power shunts and ground shunts. The shunts are to supply an electrical current from the capacitors to an integrated circuit device. The socket pin area may be surrounded by a metal fence serving as to lessen electromagnetic interference and as a ground and/or signal reference. The fence may be divided into sub-areas each comprising a coaxial differential signal pin opening pair. In alternate designs, an elongated power bar may serve as a power or ground shunt and may be used with several capacitors.

Abstract: An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits.

Abstract: A socket coupled to a circuit board to receive a package of microelectronic device has one or more electrical contacts coupled to its outer surfaces. Each contact provides a low inductance shunt connection from the side of the package to the circuit board. The contact includes multiple adjacent, electrically conductive members, each including a rigid portion and a flexible portion projecting from the rigid portion. The flexible portion is positioned to be in physical contact with a corresponding electrical conductor on an outer surface of the package when the package is coupled to the socket. At least one adjacent pair of the electrically conductive members conduct current in opposite directions to provide mutual inductance. The contact further includes a dielectric layer sandwiched between each two adjacent rigid portions of the conductive members.

Abstract: Arrangements are used for minimizing signal path discontinuities.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: A multilayer capacitor is constructed to minimize equivalent series inductance (ESL) and to achieve large capacitance. The capacitor includes first and second main go surface terminal electrodes provided on a first main surface of the main body of the multilayer capacitor. First and second side surface terminal electrodes are disposed on four side surfaces of the main body. The main body is divided into a low ESL section of the first main-surface side and a high capacitance section of the second main-surface side. In the low ESL section, in addition to first and second low ESL internal electrodes, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode are provided.

Abstract: Arrangements are used to improve noise immunity of differential signals.

Abstract: A socket and fabrication method provide enhanced performance. The socket includes a base, and a plurality of signal contacts disposed within the base. A grounding fence is also disposed within the base such that the grounding fence laterally isolates the signal contacts from one another. The use of a grounding fence therefore enables elimination or significant reduction of ground contacts and therefore provides more signaling opportunities for a given amount of real estate.

Abstract: The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device.

Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.

Abstract: An apparatus includes a socket and a housing. The socket and the housing can define an interior region for receiving an integrated circuit package. The housing includes a conductive member with a first portion exposed adjacent a bottom surface of the housing and a second portion at a side surface adjacent the interior region. The first portion can be electrically in contact with a printed circuit board. The second portion can be electrically in contact with a conductive member at a side surface of the integrated circuit package.

Abstract: In one embodiment of the invention, an embedded enclosure includes a power plane and first and second ground planes. The power plane has a power surface and a power periphery, and couples power to signals of an integrated circuit operating at a fundamental frequency. The first and second ground planes have first and second ground surfaces and first and second ground peripheries, respectively. The first and second ground planes couple ground to the signals. The first and second ground planes are separated from the power plane by first and second distances, respectively. The first and second ground surfaces are larger than the power surface. The first and second ground peripheries extend at least third and fourth distances from the power periphery, respectively. The third and fourth distances are N and M times larger than the first and second distances, respectively.

Abstract: An electronic circuit package (400, FIG. 4) includes one or more trench vias (404, FIG. 4). Each trench via makes electrical contact with one or more terminals (526, FIG. 5) of a discrete device (520, FIG. 5) embedded within the package. A trench via can extend to a surface of the package, or one or more conventional vias (620, FIG. 6) formed within layers (602, FIG. 6) above or below the trench via can electrically connect the trench via, and thus the discrete device, to the surface of the package. The discrete device (520, FIG. 5) can be a capacitor, in one embodiment, providing decoupling capacitance to an integrated circuit load. Besides being implemented in a package, the trench vias also could be implemented in other types of electronic circuit housings (e.g., interposers, sockets, and printed circuit boards).

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: An apparatus includes a package having a first surface and a conductive contact exposed at the first surface. A capacitor is inside the package. The capacitor has a first conductive contact exposed at a first surface of the capacitor. The first conductive contact has a first portion spanning a width of the first surface of the capacitor. The first surface of the capacitor is substantially parallel to the first surface of the package. A conductive path connects the first portion of the first conductive contact of the capacitor to the first conductive contact proximate the first surface of the package.

Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.

Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material.

Abstract: A design for capacitor terminals that includes connections to lowermost power and ground plates located within the bottom perimeter of the capacitor itself, for reducing loop inductance. The capacitor is particularly useful in combination with a circuit board, and especially in the power delivery system for a microprocessor.