Patents by Inventor David G. Figueroa

David G. Figueroa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020066951
    Abstract: The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.
    Type: Application
    Filed: December 4, 2000
    Publication date: June 6, 2002
    Inventors: Yuan-Liang Li, David G. Figueroa, Priyavadan R. Patel
  • Patent number: 6388207
    Abstract: To accommodate the operational and structural requirements of high performance integrated circuits, an integrated circuit package includes conductive trenches that are formed within a substrate. The trenches provide increased current carrying capacity, lower inductance, higher capacitance, and single and/or dual reference planes for signal conductors. Trench structures can be provided at various locations within the substrate, such as adjacent to signal conductors and embedded capacitors, as well as on the substrate periphery to couple the package to a socket. Trenches can be formed by routing, drilling, imprinting, and/or microperforation. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: May 14, 2002
    Assignee: Intel Corporation
    Inventors: David G. Figueroa, Michael Walk, Yuan-Liang Li, Robert L. Sankman
  • Patent number: 6366467
    Abstract: An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: P. R. Patel, Yuan-Liang Li, David G. Figueroa, Shamala Chickamenahalli, Huong T. Do
  • Patent number: 6346743
    Abstract: A capacitor assembly having one or more capacitors embedded in the core layer of a package having integrated circuits (ICs) mounted thereon. Each embedded capacitor has plural pairs of first and second electrodes and the package core layer has plural sets of first and second vias dispersed over the pairs of electrodes and being connected thereto. A metal layer is provided on the core layer and includes a first portion having at least one metal strip and a second portion, electrically isolated from each strip. Each metal strip is positioned such that it is extended to overlie both the first electrode of a distinct pair of electrodes and the second electrode of an adjacent, succeeding pair of electrodes and effects a mutual electrical connection between them through first and second vias associated therewith, respectively.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: February 12, 2002
    Assignee: Intel Corp.
    Inventors: David G. Figueroa, Yuan-Liang Li, Chee-Yee Chung