Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract: The present invention relates to a power socket for a microelectronic device that, in one embodiment, uses a low-resistance power and ground terminal configuration. In another embodiment, a low-resistance power and ground terminal configuration is combined on the power socket with a vertically oriented interdigital capacitor that is used to lower inductance. By this combination a significantly lowered impedance is achieved during operation of the microelectronic device. The capacitor may include plates that are vertically oriented relative to the major planar surface of the socket faces and capacitors may be located between a power and a ground contact, between two power contacts, or between two ground contacts.

Abstract: A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer.

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A method for fabricating a socket (300, FIG. 3) includes fabricating a conductive structure (310, FIG. 3) and embedding the conductive structure in a housing (302). The housing includes multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). In one embodiment, the embedded conductive structure (310) is electrically connected to one or more ground conducting contacts (708, FIG. 7B). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4).

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: An integrated circuit socket with capacitors and shunts is disclosed. According to one embodiment of the invention, a socket is divided into a shunt area, a socket pin area, and a land side capacitor area. The shunt area may contain a variable number of power shunts, ground shunts, and capacitors. The capacitors are connected across, and serve to decouple, power shunts and ground shunts. The shunts are to supply an electrical current from the capacitors to an integrated circuit device. The socket pin area may be surrounded by a metal fence serving as to lessen electromagnetic interference and as a ground and/or signal reference. The fence may be divided into sub-areas each comprising a coaxial differential signal pin opening pair. In alternate designs, an elongated power bar may serve as a power or ground shunt and may be used with several capacitors.

Abstract: A socket and fabrication method provide enhanced performance. The socket includes a base, and a plurality of signal contacts disposed within the base. A grounding fence is also disposed within the base such that the grounding fence laterally isolates the signal contacts from one another. The use of a grounding fence therefore enables elimination or significant reduction of ground contacts and therefore provides more signaling opportunities for a given amount of real estate.

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

Abstract: A socket and fabrication method provide enhanced performance. The socket includes a base, and a plurality of signal contacts disposed within the base. A grounding fence is also disposed within the base such that the grounding fence laterally isolates the signal contacts from one another. The use of a grounding fence therefore enables elimination or significant reduction of ground contacts and therefore provides more signaling opportunities for a given amount of real estate.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: A circuit board including a conductive plane, a first via and a second via. The first and second vias extend through the conductive plane such that there is no conductive material between the first and second vias within the conductive plane.

Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

Abstract: An electronic package, such as an integrated circuit package, includes a cavity (310, 410 FIGS. 3, 4) on the back side of the package, which is the same side on which connectors (304, 408, FIGS. 3, 4) to a next level of interconnect are located. Within the cavity are contacts (312, 412, FIGS. 3, 4), which enable one or more discrete capacitors (302, 402, FIGS. 3, 4) to be electrically connected to the package. The package provides a very low vertical inductance path between the capacitors and an integrated circuit (314, FIG. 3) mounted on the front side of the package.

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract: A socket coupled to a circuit board to receive a package of microelectronic device has one or more electrical contacts coupled to its outer surfaces. Each contact provides a low inductance shunt connection from the side of the package to the circuit board. The contact includes multiple adjacent, electrically conductive members, each including a rigid portion and a flexible portion projecting from the rigid portion. The flexible portion is positioned to be in physical contact with a corresponding electrical conductor on an outer surface of the package when the package is coupled to the socket. At least one adjacent pair of the electrically conductive members conduct current in opposite directions to provide mutual inductance. The contact further includes a dielectric layer sandwiched between each two adjacent rigid portions of the conductive members.

Abstract: An integrated circuit socket includes one or more cavities formed in a top surface of the socket, where the one or more cavities are formed in a region over which an integrated circuit can be placed. Multiple conductive contacts are attached to the socket, where each contact includes a first member that extends into one of the cavities, and a second member that provides at least part of a conductive path between the first member and the socket. The first member at least partially holds in place a discrete device inserted into the cavity. An integrated circuit package or interposer attached to the top surface over the cavity also can at least partially hold the discrete device in place. The first member makes electrical contact with the discrete device, thus completing a conductive path between the discrete device and the integrated circuit.