Patents by Inventor Dean A. Klein

Dean A. Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8850112
    Abstract: A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data from the hard disk drive, the control circuit first determines if the requested read data are stored in the non-volatile memory. If so, the requested read data are provided from the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. The volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: September 30, 2014
    Assignee: Round Rock Research, LLC
    Inventor: Dean A. Klein
  • Patent number: 8832360
    Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Dean Klein
  • Publication number: 20140181613
    Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 26, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20140112087
    Abstract: A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by logically ORing, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.
    Type: Application
    Filed: December 24, 2013
    Publication date: April 24, 2014
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Dean A. Klein
  • Patent number: 8689077
    Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20140082375
    Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a nonvolatile memory. The key may also be derived at least in part from user input to the computer.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 20, 2014
    Inventor: Dean A. Klein
  • Publication number: 20140025923
    Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20140013035
    Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.
    Type: Application
    Filed: May 24, 2013
    Publication date: January 9, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Dean KLEIN
  • Patent number: 8619485
    Abstract: A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: December 31, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Dean A. Klein
  • Patent number: 8587981
    Abstract: Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The checkpoint memory may be located on a same semiconductor substrate or circuit board as the processor. The checkpoint memory may be located on a same semiconductor substrate as a main memory used by the processor during normal operation. The checkpoint memory may be included in a memory hub configuration, with a checkpoint memory hub provided for access to the checkpoint memory.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: November 19, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20130283230
    Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.
    Type: Application
    Filed: June 18, 2013
    Publication date: October 24, 2013
    Inventor: Dean A. Klein
  • Patent number: 8533491
    Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a nonvolatile memory. The key may also be derived at least in part from user input to the computer.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: September 10, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Dean A. Klein
  • Patent number: 8493797
    Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: July 23, 2013
    Assignee: Round Rock Research, LLC
    Inventor: Dean A. Klein
  • Patent number: 8468506
    Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: June 18, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 8452916
    Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dean Klein
  • Patent number: 8446783
    Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 21, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20130003467
    Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 3, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20120297129
    Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 22, 2012
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventor: Dean A. Klein
  • Publication number: 20120284454
    Abstract: A master memory controller comprises a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.
    Type: Application
    Filed: July 19, 2012
    Publication date: November 8, 2012
    Inventor: Dean KLEIN
  • Patent number: 8279683
    Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein