Patents by Inventor Dean A. Klein

Dean A. Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7615729
    Abstract: A method and apparatus for focusing an image on a pixel array. The method includes the steps of continuously changing the distance between a lens and a pixel array between a first distance and a second distance and obtaining an image projected onto the pixel array through the distance is changing. The apparatus includes a lens and an electromechanical structure to continuously change the distance between the lens and the pixel array between the first distance and the second distance.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: November 10, 2009
    Assignee: Aptina Imaging Corporation
    Inventor: Dean A. Klein
  • Publication number: 20090265504
    Abstract: Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The checkpoint memory may be located on a same semiconductor substrate or circuit board as the processor. The checkpoint memory may be located on a same semiconductor substrate as a main memory used by the processor during normal operation. The checkpoint memory may be included in a memory hub configuration, with a checkpoint memory hub provided for access to the checkpoint memory.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 22, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20090265509
    Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
    Type: Application
    Filed: July 2, 2009
    Publication date: October 22, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7595844
    Abstract: One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees the often-overburdened central processing unit from performing this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as a method thr compressing video data in a computer system. This method includes receiving a stream of data from a current video frame in the computer system. It also includes computing a difference frame from the current video frame and a previous video frame “on-the-fly” as the current video frame streams into the computer system. The method additionally includes storing the difference frame in a memory in the computer system.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: September 29, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7583551
    Abstract: A memory devices provide signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: September 1, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7564722
    Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: July 21, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7558142
    Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: July 7, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20090146047
    Abstract: A method and apparatus for focusing an image on a pixel array. The method includes the steps of continuously changing the distance between a lens and a pixel array between a first distance and a second distance and obtaining an image projected onto the pixel array through the distance is changing. The apparatus includes a lens and an electromechanical structure to continuously change the distance between the lens and the pixel array between the first distance and the second distance.
    Type: Application
    Filed: December 10, 2007
    Publication date: June 11, 2009
    Inventor: Dean A. Klein
  • Publication number: 20090147608
    Abstract: A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.
    Type: Application
    Filed: February 6, 2009
    Publication date: June 11, 2009
    Inventor: Dean A. Klein
  • Publication number: 20090132790
    Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.
    Type: Application
    Filed: January 28, 2009
    Publication date: May 21, 2009
    Inventor: Dean A. Klein
  • Patent number: 7526713
    Abstract: A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words written to the DRAM, and thereby achieves a low syndrome bit overhead. The memory controller may write data words to the DRAM having less than 128 bits by first reading 4 32-bit words from the DRAM, substituting the write data for a corresponding number of bits of read data, and writing the new 128-bit word to the DRAM by writing 4 32-bit words.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: April 28, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20090090924
    Abstract: Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a device. The optical element is formed by applying a force to lateral portions of a liquid material layer formed below an elastomeric material layer such that the liquid material layer has a radius of curvature sufficient to direct light to a light sensitive portion of the device, after which the liquid material layer is exposed to conditions which maintain the radius of curvature after the lateral force is removed.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 9, 2009
    Inventors: Dean A. Klein, Ian Blasch
  • Patent number: 7504608
    Abstract: A lens assembly and method of adjusting a lens assembly using an electrically active polymer element. The assembly comprises a lens; a pixel array for receiving an image through said lens via an optical path; a moveable element for changing the optical properties of said optical path; and at least one electrically active polymer for changing volume in response to an applied voltage, said polymer being coupled to said moveable element such that changes in volume of said polymer causes movement of said moveable element.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: March 17, 2009
    Assignee: Aptina Imaging Corporation
    Inventor: Dean A. Klein
  • Patent number: 7491243
    Abstract: The present invention provides a method of modifying the lower esophagus by injecting biocompatible particles in a biocompatible carrier into a submucosal tissue site of the lower esophagus of a patient. The method may be used to treat gastroesophageal reflux disease by optimizing the closing function of the lower esophageal sphincter.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: February 17, 2009
    Assignee: Carbon Medical Technologies
    Inventor: Dean A. Klein
  • Patent number: 7490210
    Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20090024884
    Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.
    Type: Application
    Filed: September 22, 2008
    Publication date: January 22, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7461320
    Abstract: A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching the DRAM to the low power refresh mode, the processor identifies a region of an array of DRAM cells that contains essential data that needs to be protected from such data retention errors. The processor then reads data from the identified region, and either the DRAM or the memory controller generates error checking and correcting syndromes from the read data. The syndromes are stored in the DRAM, and the low power refresh mode is then entered. Upon exiting the low power refresh mode, the processor again reads the data from the identified region, and the read data is checked and corrected using the syndromes.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: December 2, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7457205
    Abstract: An optical disk changer that is capable of automatically playing both sides of a dual-sided optical disk. By coordinated rotation and delivery of disks taken from a linear disk storage bin, both sides of a dual-sided optical disk can be automatically accessed.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: November 25, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7450410
    Abstract: The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: November 11, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7447973
    Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: November 4, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein