Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters

Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors atop at least a portion of the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 150 nm misalignment, and where at least one of the second transistors is a junction-less transistor.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device including: a first level including logic circuits, the logic circuits include a plurality of first single crystal transistors and a first metal layer; a second level including a plurality of second transistors, where the second level includes memory cells including the plurality of second transistors; a second metal layer atop the second level; where the plurality of second transistors are junction-less transistors, where at least one of the plurality of second transistors includes polysilicon, where the memory cells are structured as a plurality of at least sixteen sub-arrays, where each of the sub-arrays is independently controlled, where at least one of the plurality of at least sixteen sub-arrays is at least partially atop at least one of the logic circuits, and where the at least one of the logic circuits is designed to control at least one of the plurality of at least sixteen sub-arrays.

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of first logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors atop the at least one metal layer; a plurality of third transistors atop the second transistors; a top metal layer atop the third transistors; and a memory array including wordlines, where the memory array includes at least four rows by four columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.

Abstract: A 3D device including: a first level including first single crystal transistors overlaid by a second level including second single crystal transistors; a third level including third single crystal transistors, the second level is overlaid by the third level; a fourth level including fourth single crystal transistors, the third level is overlaid by the fourth level; first bond regions including first oxide to oxide bonds, where the first bond regions are between the first level and the second level; second bond regions including second oxide to oxide bonds, where the second bond regions are between the second level and the third level; and third bond regions including third oxide to oxide bonds, where the third bond regions are between the third level and the fourth level, where the second level, third level, and fourth level each include one array of memory cells, and where the one array of memory cells is a DRAM type memory.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the device includes at least a first logic circuit and a second logic circuit, and where the device includes a control function adapted to use the second logic circuit as a redundancy for the first logic circuit so to overcome a fault in the first logic circuit.

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an optical waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

Abstract: An automated food making apparatus is described. An automated food making apparatus can include: a carousel; a dispensing apparatus shared among a plurality of canisters on the carousel, wherein at least one canister includes a paddle; and wherein the dispensing apparatus is configured to rotate the canister's paddle to dispense ingredients stored in the canister. A dispensing mechanism for an automated food making apparatus can include: an actuator arm; a motor that is adapted to rotate the actuator arm; one or more magnets embedded in the actuator arm; and one or more sensors configured to detect position of the actuator arm; wherein the actuator arm dispenses ingredients by rotating a pin located on a canister.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an optical waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include at least two side gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device, the device including: a first level overlaid by a second level overlaid by a third level overlaid by a fourth level, where the second level includes an array of first memory cells, the first memory cells including first transistors, the first transistors including first sources, first gates, and first drains, where each of the first transistors includes a single the first source, a single the first gate, and a single the first drain, where the third level includes an array of second memory cells, the second memory cells including second transistors, the second transistors including second sources, second gates, and second drains, where each of the second transistors includes a single the second source, a single the second gate, and a single the second drain, where at least one of the first memory cells is self-aligned to at least one of the second memory cells, being processed following the same lithography step; vertically oriented word-lines adapted to control a plurality of the f

Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding; and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.

Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including at least one LED driving circuit; a second single crystal layer including a first plurality of light emitting diodes (LEDs), where the second single crystal layer is on top of the first single crystal layer, where the second single crystal layer includes at least ten individual first LED pixels; and a second plurality of light emitting diodes (LEDs), where the 3D micro display includes an oxide to oxide bonding structure.

Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.