Patents by Inventor Deepak C. Sekar

Deepak C. Sekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220230906
    Abstract: A 3D semiconductor device including: a first level including a single crystal layer and plurality of first transistors; a first metal layer including interconnects between first transistors, where the interconnects between the first transistors includes forming logic gates; a second metal layer atop at least a portion of the first metal layer, second transistors which are vertically oriented, are also atop a portion of the second metal layer; where at least eight of the first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the second transistors is at least partially directly atop of the NAND logic structure; and a third metal layer atop at least a portion of the second transistors, where the second metal layer is aligned to the first metal layer with a less than 150 nm misalignment.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 21, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220223459
    Abstract: A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed on top of the control circuits; performing a first etch step including etching first holes within the second level; and performing additional processing steps (including Atomic Layer Deposition) to form a plurality of memory cells within the second level, where each memory cell includes at least one second transistor, where making the second level includes forming lithography holes atop of the first alignment marks which enables performing lithography steps aligned to the first alignment marks, including at least the first etch step above.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 14, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220223458
    Abstract: A 3D semiconductor device including: a first single-crystal layer including a plurality of first transistors; at least one first metal layer disposed atop the plurality of first transistors; a second metal layer disposed atop the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed atop the plurality of fourth transistors; a fourth metal layer disposed atop the third metal layer; a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 14, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220208594
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer disposed above the plurality of first transistors; a second metal layer disposed above the at least one first metal layer; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the plurality of second transistors; a plurality of fourth transistors disposed atop the plurality of third transistors; a third metal layer disposed above the plurality of fourth transistors; a fourth metal layer disposed above the third metal layer; and a plurality of connecting metal paths from the fourth metal layer or the third metal layer to the second metal layer, where the device includes an array of memory cells, and where at least one of the memory cells includes one of the plurality of third transistors.
    Type: Application
    Filed: March 19, 2022
    Publication date: June 30, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220208812
    Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes at least one LED driving circuit; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer, where the second level is disposed on top of the first level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.
    Type: Application
    Filed: March 19, 2022
    Publication date: June 30, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Patent number: 11374118
    Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: June 28, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
  • Patent number: 11374042
    Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes at least one LED driving circuit; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer, where the second level is disposed on top of the first level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.
    Type: Grant
    Filed: March 19, 2022
    Date of Patent: June 28, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Publication number: 20220181186
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least two metal layers; a plurality of logic gates including the at least two metal layers interconnecting the plurality of first transistors; a plurality of second transistors disposed atop the at least two metal layers; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least two rows by two columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, and where at least one of the second transistors include a metal gate.
    Type: Application
    Filed: February 20, 2022
    Publication date: June 9, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220181187
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first single crystal transistors; a first metal layer; a second metal layer disposed atop the first metal layer; second transistors disposed atop of the second metal layer; third transistors disposed atop of the second transistors, where at least one of the third transistors includes at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate, and where a distance from at least one of the third transistors to at least one of the second transistors is less than 1 micron.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11355380
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 7, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11355381
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second level includes an array of memory cells, and where each of the memory cells includes at least one recessed-channel-array-transistor (RCAT).
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: June 7, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220165602
    Abstract: A method for producing a 3D memory device, including: providing a first level including a single crystal layer and control circuits, the control circuits include a plurality of first single crystal transistors; forming at least one second level disposed above the first level; processing to form a plurality of second transistors, where the processing includes forming a plurality of memory cells, each of the plurality of memory cells includes at least one of the plurality of second transistors, where the control circuits control the plurality of memory cells, where at least one of the plurality of memory cells is at least partially atop a portion of the control circuits, where processing the control circuits accounts for a thermal budget associated with processing of the second transistors by adjusting annealing of the first transistors accordingly; processing to replace gate material of at least one of the plurality of second transistors.
    Type: Application
    Filed: February 12, 2022
    Publication date: May 26, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11342214
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: May 24, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11335731
    Abstract: A semiconductor device, the device comprising: a plurality of transistors, wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain, wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain, wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain, wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and wherein said first single crystal channel is self-aligned to said second single crystal channel being processed following the same lithography step.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: May 17, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 11327227
    Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: October 3, 2021
    Date of Patent: May 10, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20220130905
    Abstract: A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 11315965
    Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including a first plurality of light emitting diodes (LEDs); a second single crystal layer including a second plurality of light emitting diodes (LEDs), where the first single crystal layer includes at least ten individual first LED pixels, where the second single crystal layer includes at least ten individual second LED pixels, where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm; and further including a third single crystal layer including at least one LED driving circuit.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: April 26, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Patent number: 11315980
    Abstract: A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the plurality of transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the plurality of transistors includes a fourth single crystal source, channel, and drain, and where the first single crystal source or drain, and the second single crystal source or drain each include n+ doped regions.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 26, 2022
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Publication number: 20220122877
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.
    Type: Application
    Filed: December 31, 2021
    Publication date: April 21, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20220093440
    Abstract: A semiconductor device, the device including: a first single crystal substrate and plurality of logic circuits, where the first single crystal substrate has a device area, where the device area is significantly larger than a reticle size, where the plurality of logic circuits include an array of processors, where the plurality of logic circuits include a first logic circuit, a second logic circuit, and third logic circuit, where the plurality of logic circuits include switching circuits to support replacing the first logic circuit and the second logic circuit by the third logic circuit; and a built-in-test-circuit (“BIST”), where the built-in-test-circuit is connected to test at least the first logic circuit and the second logic circuit.
    Type: Application
    Filed: December 5, 2021
    Publication date: March 24, 2022
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar