Patents by Inventor Deepak C. Sekar
Deepak C. Sekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220093440Abstract: A semiconductor device, the device including: a first single crystal substrate and plurality of logic circuits, where the first single crystal substrate has a device area, where the device area is significantly larger than a reticle size, where the plurality of logic circuits include an array of processors, where the plurality of logic circuits include a first logic circuit, a second logic circuit, and third logic circuit, where the plurality of logic circuits include switching circuits to support replacing the first logic circuit and the second logic circuit by the third logic circuit; and a built-in-test-circuit (“BIST”), where the built-in-test-circuit is connected to test at least the first logic circuit and the second logic circuit.Type: ApplicationFiled: December 5, 2021Publication date: March 24, 2022Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20220084869Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; second metal layer overlaying the first metal layer, and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include a High-k metal gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Patent number: 11257867Abstract: A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal channel, where at least one of the plurality of transistors includes a second single crystal channel, where the second single crystal channel is disposed above the first single crystal channel, where at least one of the plurality of transistors includes a third single crystal channel, where the third single crystal channel is disposed above the second single crystal channel, where at least one of the plurality of transistors includes a fourth single crystal channel, and where the fourth single crystal channel is disposed above the third single crystal channel; and at least one region of oxide to oxide bonds.Type: GrantFiled: December 5, 2021Date of Patent: February 22, 2022Assignee: MONOLITHIC 3D INC.Inventors: Deepak C. Sekar, Zvi Or-Bach
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Publication number: 20220028759Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via has a diameter of less than 400 nm and greater than 5 nm.Type: ApplicationFiled: October 2, 2021Publication date: January 27, 2022Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20220026636Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.Type: ApplicationFiled: October 3, 2021Publication date: January 27, 2022Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Patent number: 11227897Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and first alignment marks; forming memory control circuits including first single crystal transistors, where the first single crystal transistors include portions of the single crystal layer; forming at least one second level above the first level; performing a first etch step including etching lithography windows within the at least one second level; performing a first lithographic step over the at least one second level aligned to the first alignment marks; and performing additional processing steps to form a plurality of first memory cells within the at last one second level, where each of the plurality of first memory cells include one of a plurality of second transistors, and where the plurality of second transistors are aligned to the first alignment marks with a less than 40 nm alignment error.Type: GrantFiled: August 14, 2021Date of Patent: January 18, 2022Assignee: MONOLITHIC 3D INC.Inventors: Deepak C. Sekar, Zvi Or-Bach
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Publication number: 20220013556Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including a first plurality of light emitting diodes (LEDs); a second single crystal layer including a second plurality of light emitting diodes (LEDs), where the first single crystal layer includes at least ten individual first LED pixels, where the second single crystal layer includes at least ten individual second LED pixels, where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm; and further including a third single crystal layer including at least one LED driving circuit.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar
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Patent number: 11217472Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, where the bonded includes at least one oxide to oxide bond, and where the bonded includes at least one metal to metal bond.Type: GrantFiled: April 18, 2021Date of Patent: January 4, 2022Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210407842Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Patent number: 11211279Abstract: A method for processing a 3D integrated circuit, the method including: providing a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; processing a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; then forming a bonded structure by bonding the second level to the first level, where the bonding includes metal to metal bonding, where the bonding includes oxide to oxide bonding; and then performing a lithography process to define dice lines for the bonded structure; and etching the dice lines.Type: GrantFiled: January 3, 2021Date of Patent: December 28, 2021Assignee: MONOLITHIC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210375995Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and first alignment marks; forming memory control circuits including first single crystal transistors, where the first single crystal transistors include portions of the single crystal layer; forming at least one second level above the first level; performing a first etch step including etching lithography windows within the at least one second level; performing a first lithographic step over the at least one second level aligned to the first alignment marks; and performing additional processing steps to form a plurality of first memory cells within the at last one second level, where each of the plurality of first memory cells include one of a plurality of second transistors, and where the plurality of second transistors are aligned to the first alignment marks with a less than 40 nm alignment error.Type: ApplicationFiled: August 14, 2021Publication date: December 2, 2021Applicant: Monolithic 3D Inc.Inventors: Deepak C. Sekar, Zvi Or-Bach
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Publication number: 20210375972Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.Type: ApplicationFiled: August 14, 2021Publication date: December 2, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Publication number: 20210358794Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a second level including a plurality of second transistors, where the second level overlays the first level, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the plurality of second transistors is at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the second level, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.Type: ApplicationFiled: July 25, 2021Publication date: November 18, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210343570Abstract: A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Publication number: 20210343571Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing additional processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one of the first memory cells is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with the processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Applicant: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Patent number: 11164770Abstract: A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks.Type: GrantFiled: July 12, 2021Date of Patent: November 2, 2021Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
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Patent number: 11164811Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, and where the bonded includes at least one oxide to oxide bond.Type: GrantFiled: May 6, 2021Date of Patent: November 2, 2021Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Patent number: 11164898Abstract: A 3D micro display, the 3D micro display including: a first single crystal layer including a first plurality of light emitting diodes (LEDs), a second single crystal layer including a second plurality of light emitting diodes (LEDs), where the first single crystal layer includes at least ten individual first LED pixels, where the second single crystal layer includes at least ten individual second LED pixels, where the first plurality of light emitting diodes (LEDs) emits a first light with a first wavelength, where the second plurality of light emitting diodes (LEDs) emits a second light with a second wavelength, where the first wavelength and the second wavelength differ by greater than 10 nm, and where the 3D micro display includes an oxide to oxide bonding structure.Type: GrantFiled: March 29, 2021Date of Patent: November 2, 2021Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar
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Patent number: 11163112Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.Type: GrantFiled: May 25, 2021Date of Patent: November 2, 2021Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Patent number: 11158674Abstract: A method for producing a 3D memory device, the method comprising: providing a first level comprising a single crystal layer; forming at least one second level above said first level; performing a first etch step comprising etching holes within said second level; forming at least one third level above said at least one second level; performing a second etch step comprising etching holes within said third level; performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein each of said first memory cells comprise one first transistor, wherein each of said second memory cells comprise one second transistor, wherein at least one of said first or second transistors has a channel, a source and a drain having the same doping type, and wherein said forming at least one third level comprises forming a window within said third level to allow lithography alignment through said third level to an alignment mType: GrantFiled: December 14, 2020Date of Patent: October 26, 2021Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist