Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: Techniques are provided for non-volatile storage self-detecting that a heating event has occurred to the non-volatile storage. One example of the heating event is an Infrared (IR) reflow process. In one aspect, a block of memory cells in a memory device are put through a number of program/erase cycles. A group of the memory cells in the cycled block are programmed to a reference threshold voltage distribution. Some time may pass after programming the cycled block. The memory device self-detects that there has been a heating event in response to a shift in the reference VT distribution being more than an allowed amount. The memory device may switch from a first programming mode to a second programming mode in response to detecting that the heating event has occurred.

Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.

Abstract: A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower threshold voltages. A compensation pass bias can be reduced as the state being sensed at a selected word line increases to account for the different effects. A compensation pass bias for an adjacent word line may be reduced with the application of larger read reference voltages to a selected word line. Other variations to a compensation pass bias are provided.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for program sequencing. An apparatus includes a block of non-volatile storage cells having a plurality of word lines. The word lines are organized into a monotonically increasing sequence. The apparatus includes a controller for the block. The controller is configured to program a set of storage cells of a word line to one or more storage states above a predetermined threshold and to program a set of storage cells of a previous word line adjacent to and before the word line in the sequence, to one or more storage states below the predetermined threshold after programming the set or storage cells of the word line to the one or more storage states above the predetermined threshold.

Abstract: Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification.

Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.

Abstract: A data storage device includes a memory including multiple storage elements. The data storage device also includes circuitry configured to determine, for a particular storage element of the multiple storage elements, an indicator associated with a threshold voltage temperature dependence (TVTD) of the particular storage element.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: A non-volatile storage system includes defect detection and early program termination. The system commences programming of a plurality of non-volatile memory cells, determines that a defect condition exists and, in response to determining that the defect condition exists, terminates the programming of the plurality of memory cells prior to completion of programming.

Abstract: Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase. For a memory cell in the fine phase that has been verified to have reached the fine phase verify level, the memory cell will be inhibited from further programming.

Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.

Abstract: A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.

Abstract: Methods and systems for verifying two or more programming states at the same time are described. During a program verify operation, two or more memory cell threshold voltage levels may be concurrently verified by applying a word line voltage to a plurality of memory cells, applying two or more different bit line voltages to the plurality of memory cells, and sensing the plurality of memory cells while the two or more different bit line voltages are applied to the plurality of memory cells. The bit line voltages applied during the program verify operation may allow a first set of the plurality of memory cells to be sensed at a first voltage level while a second set of the plurality of memory cells are sensed at a second voltage level different from the first voltage level.

Abstract: Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase.

Abstract: A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of memory cells based on programming performance. Based on the classifying, the control circuit applies different programming signals to different subsets of the memory cells being programmed to a common data state.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the memory cells. While applying the reference voltage to the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.

Abstract: A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.