Patents by Inventor Deepanshu Dutta
Deepanshu Dutta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10467134Abstract: Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature.Type: GrantFiled: August 25, 2016Date of Patent: November 5, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Navneeth Kankani, Linh Truong, Sarath Puthenthermadam, Deepanshu Dutta
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Patent number: 10468111Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.Type: GrantFiled: April 30, 2018Date of Patent: November 5, 2019Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20190333588Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Xiang YANG, Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20190318792Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.Type: ApplicationFiled: April 13, 2018Publication date: October 17, 2019Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20190304549Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Inventors: Xiang YANG, Huai-yuan TSENG, Deepanshu DUTTA
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Publication number: 20190295669Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.Type: ApplicationFiled: March 22, 2018Publication date: September 26, 2019Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Piyush Dak, Wei Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Mohan Dunga
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Publication number: 20190272871Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.Type: ApplicationFiled: March 2, 2018Publication date: September 5, 2019Applicant: SanDIsk Technologies LLCInventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20190267096Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. When the sense circuit is connected to the unselected bit line during the sense operation, the sense circuit is locked out in order to reduce current consumption. However, noise from the locked out sense circuit may be transmitted to the sense circuits connected to the selected bit lines through adjacent bit line coupling. In order to reduce the effect of the noise, charge transfer from the sense node may be blocked from passing to the unselected bit lines. Or, charge may be drained from the sense node, thereby preventing the charge from passing to the unselected bit lines.Type: ApplicationFiled: February 28, 2018Publication date: August 29, 2019Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Stanley Jeong, Wei Zhao, Huai-yuan Tseng, Deepanshu Dutta
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Publication number: 20190252030Abstract: Disclosed herein is related to a memory device and a method of verifying a programmed status of the memory device. The memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.Type: ApplicationFiled: April 26, 2018Publication date: August 15, 2019Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta, Jianzhi Wu, Gerrit Jan Hemink
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Patent number: 10381083Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.Type: GrantFiled: June 25, 2018Date of Patent: August 13, 2019Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Kun-Huan Shih, Matthias Baenninger, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
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Publication number: 20190244673Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.Type: ApplicationFiled: June 25, 2018Publication date: August 8, 2019Applicant: SanDisk Technologies LLCInventors: XIANG YANG, DEEPANSHU DUTTA, HUAI-YUAN TSENG
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Publication number: 20190214100Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.Type: ApplicationFiled: January 5, 2018Publication date: July 11, 2019Applicant: SanDisk Technologies LLCInventors: Sarath Puthenthermadam, Deepanshu Dutta, Long Pham
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Patent number: 10229744Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.Type: GrantFiled: November 17, 2017Date of Patent: March 12, 2019Assignee: SanDisk Technologies LLCInventors: Deepanshu Dutta, Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheah, Sarath Puthenthermadam
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Patent number: 10217520Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.Type: GrantFiled: August 24, 2017Date of Patent: February 26, 2019Assignee: SanDisk Technologies LLCInventors: Muhammad Masuduzzaman, Deepanshu Dutta, Jong Yuh
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Patent number: 10157680Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.Type: GrantFiled: December 20, 2016Date of Patent: December 18, 2018Assignee: SANDISK TECHNOLOGIES LLPInventors: Xiang Yang, Huai-Yuan Tseng, Xiaochang Miao, Deepanshu Dutta
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Publication number: 20180254090Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.Type: ApplicationFiled: November 17, 2017Publication date: September 6, 2018Applicant: SanDisk Technologies LLCInventors: Deepanshu Dutta, Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheah, Sarath Puthenthermadam
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Patent number: 10068656Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.Type: GrantFiled: December 27, 2016Date of Patent: September 4, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Sarath Puthenthermadam, Chris Yip
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Patent number: 10026486Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.Type: GrantFiled: March 6, 2017Date of Patent: July 17, 2018Assignee: SanDisk Technologies LLCInventors: Deepanshu Dutta, Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheah, Sarath Puthenthermadam
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Patent number: 10026492Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.Type: GrantFiled: July 2, 2017Date of Patent: July 17, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepanshu Dutta, Arash Hazeghi, Huai-Yuan Tseng, Cynthia Hsu, Navneeth Kankani
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Patent number: 10014063Abstract: Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.Type: GrantFiled: October 30, 2015Date of Patent: July 3, 2018Assignee: SanDisk Technologies LLCInventors: Huai-Yuan Tseng, Deepanshu Dutta, Tai-Yuan Tseng, Grishma Shah, Muhammad Masuduzzaman
