Patents by Inventor Deepanshu Dutta

Deepanshu Dutta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for in-situ programming and read operation adjustments in a non-volatile memory
    Patent number: 10559370
    Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Piyush Dak, Wei Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Mohan Dunga
  • Non-volatile memory with countermeasure for select gate disturb
    Patent number: 10553298
    Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta
  • NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR SELECT GATE DISTURB
    Publication number: 20200035312
    Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta
  • Subgroup selection for verification
    Patent number: 10541038
    Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Xiang Yang, Zhenming Zhou, Deepanshu Dutta, Huai-Yuan Tseng
  • Non-volatile memory with countermeasure for program disturb including delayed ramp down during program verify
    Patent number: 10541037
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta
  • Single pulse verification of memory cells
    Patent number: 10535412
    Abstract: A memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: January 14, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta, Jianzhi Wu, Gerrit Jan Hemink
  • Fast detection of defective memory block to prevent neighbor plane disturb
    Patent number: 10529435
    Abstract: A bad block of memory cells is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize a threshold voltage upshift in a good block. A difference in program speeds between the blocks can be quickly detected by detecting when the memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state. If a first block passes the verify test at a reference program loop, a determination is made as to whether a second block passes the verify test within a specified number of additional program loops. If the second block meets this criterion, the program operation can continue for both blocks. However, if the second block does not meet this criterion, the program operation is terminated for the second block by isolating it from subsequent program and verify signals.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 7, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Sarath Puthenthermadam, Deepanshu Dutta, Long Pham
  • PARASITIC NOISE CONTROL DURING SENSE OPERATIONS
    Publication number: 20190392894
    Abstract: A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta, Zhenming Zhou
  • INTERLEAVED PROGRAM AND VERIFY IN NON-VOLATILE MEMORY
    Publication number: 20190392909
    Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • PROGRAMMING SELECTION DEVICES IN NON-VOLATILE MEMORY STRINGS
    Publication number: 20190392893
    Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Xiang Yang, Dengtao Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Zhongguang Xu, Yanli Zhang, Jin Liu
  • NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR PROGRAM DISTURB INCLUDING PURGE DURING PRECHARGE
    Publication number: 20190378580
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
  • SUBGROUP SELECTION FOR VERIFICATION
    Publication number: 20190378583
    Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.
    Type: Application
    Filed: November 29, 2018
    Publication date: December 12, 2019
    Inventors: Yu-Chung Lien, Xiang Yang, Zhenming Zhou, Deepanshu Dutta, Huai-Yuan Tseng
  • NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR PROGRAM DISTURB INCLUDING DELAYED RAMP DOWN DURING PROGRAM VERIFY
    Publication number: 20190378579
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Dengtao Zhao, Deepanshu Dutta
  • NON-VOLATILE MEMORY WITH COUNTERMEASURE FOR PROGRAM DISTURB INCLUDING SPIKE DURING BOOSTING
    Publication number: 20190378581
    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
  • MEMORY DEVICE WITH BIT LINES DISCONNECTED FROM NAND STRINGS FOR FAST PROGRAMMING
    Publication number: 20190371394
    Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • MEMORY DEVICE WITH CONNECTED WORD LINES FOR FAST PROGRAMMING
    Publication number: 20190371406
    Abstract: Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • MEMORY DISTURB DETECTION
    Publication number: 20190362798
    Abstract: An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.
    Type: Application
    Filed: May 26, 2018
    Publication date: November 28, 2019
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • BIT LINE VOLTAGE CONTROL FOR DAMPING MEMORY PROGRAMMING
    Publication number: 20190362799
    Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Inventors: Xiang Yang, Deepanshu Dutta, Gerrit Jan Hemink, Tai-Yuan Tseng, Yan Li
  • Ramp down sensing between program voltage and verify voltage in memory device
    Patent number: 10482984
    Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Dynamic erase loop dependent bias voltage
    Patent number: 10482985
    Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Huai-Yuan Tseng