Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.

Abstract: A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements.

Abstract: A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping between the select gates and the dummy storage elements.

Abstract: Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect.

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.

Abstract: A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate transistors is evaluated, such as in response to a program, erase or read command involving a block or sub-block of memory cells. For example, a lower tail and an upper tail of the Vth distribution can be evaluated using read voltages. If the Vth is out-of-range, such as due to read disturb, data retention loss or defects in the memory device, the block or sub-block is marked as being bad and previously-programmed data in the block or sub-block can be copied to another location. If the Vth is in range, the command can be executed. Also, a control gate voltage for the select gate transistors can be set based on a Vth metric which is obtained from the evaluation.

Abstract: A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate transistors is evaluated, such as in response to a program, erase or read command involving a block or sub-block of memory cells. For example, a lower tail and an upper tail of the Vth distribution can be evaluated using read voltages. If the Vth is out-of-range, such as due to read disturb, data retention loss or defects in the memory device, the block or sub-block is marked as being bad and previously-programmed data in the block or sub-block can be copied to another location. If the Vth is in range, the command can be executed. Also, a control gate voltage for the select gate transistors can be set based on a Vth metric which is obtained from the evaluation.

Abstract: A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.

Abstract: A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.

Abstract: Techniques are provided for programming select gate transistors in connection with the programming of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device.

Abstract: A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

Abstract: Reducing peak current and/or power consumption during erase verify of a non-volatile memory is disclosed. During an erase verify, memory cells are verified at a strict reference level that is deeper (e.g., lower threshold voltage) than a target reference level. After the strict erase verify, strings of memory cells that pass the strict erase verify are locked out from a next erase verify at the target reference level. Locked out strings do not conduct a significant current during erase verify, thus reducing peak current and/or power consumption.

Abstract: A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.

Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.

Abstract: A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements.

Abstract: Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect.

Abstract: A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a plurality of word lines connected to the non-volatile storage elements, and one or more control circuits connected to the bit lines and word lines. The one or more control circuits perform programming, verifying, reading and erasing for the non-volatile storage elements. When verifying, a first subset of bit lines connected to non-volatile storage elements are charged to allow for sensing, while a second subset of bit lines are not charged. When reading, a two strobe sensing process is selectively used to more accurately read data from the non-volatile storage elements.

Abstract: In a nonvolatile memory array that has a binary cache formed of SLC blocks and a main memory formed of MLC blocks, corrupted data along an MLC word line is corrected and relocated, along with any other data along the MLC word line, to binary cache, before it becomes uncorrectable. Subsequent reads of the relocated data directed to binary cache.

Abstract: Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.

Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.