Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

Abstract: Disclosed is a marine fuel cell-based integrated heat, electricity, and cooling supply system comprising a power supply system and a waste heat recovery system; the power supply system comprises wind turbine generator sets, solar generator sets, and a fuel cell power module; the waste heat recovery system encompasses a turbine power generation module and a lithium bromide refrigeration module; the fuel cell power module is connected to both the turbine power generation module and the lithium bromide refrigeration module; the turbine power generation module is used to generate electricity using waste heat. This approach fully exploits the waste heat from the exhaust gas generated by the fuel cell power module, resulting in a high overall energy utilization rate. The self-consumption electricity and pure hydrogen fuel for the integrated energy supply system can be obtained from solar and wind energy, ensuring low carbon emissions for the entire system.

Abstract: A holographic 3D display system based on virtual array splicing of a spatial light modulator includes a laser configured to generate a coherent light beam, first, second and third beam splitters, first and second reflectors, a shutter array, a spatial filter array, a solid lens, first and second light beam deflection elements and a spatial light modulator. The first and second beam splitters and the first reflector are configured to split the light beam generated by the laser into three parallel light beams to irradiate the shutter array. The shutter array is configured to control the three parallel light beams to sequentially pass therethrough according to a set time sequence. The three parallel light beams passing through the shutter array are expanded and collimated by the spatial filter array and the solid lens to form three parallel light beams with the same size and uniform intensity.

Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

Abstract: The invention pertains to the technical field of natural product microencapsulation, specifically focusing on a water-soluble ginger oleoresin microcapsule, along with its preparation method and applications. This invention utilizes modified starch, plant polysaccharides, and similar materials as wall materials, with ginger oleoresin serving as the core material. The ginger oleoresin microcapsules are produced through processes including molecular coating, emulsification, high-pressure homogenization, constant temperature standing, and drying. The resulting product is characterized by a high gingerol content, excellent water solubility, low spiciness in solution, and strong stability in acidic environments. It fulfills the requirements of high stability, no precipitation, low spiciness, and a pleasant thermal sensation in low pH environments, making it suitable for use in food, beverages, health foods, medicines, cosmetics, and other applications.

Abstract: A method for extracting oils from sauces while simultaneously determining fat content, peroxide value, and acid value is disclosed. The method is simple to operate and requires uncomplicated equipment. It features a short testing cycle and high efficiency, and suitable for the extraction of oils from oil-rich emulsified encapsulated sauces (such as salad dressings) with high extraction rates. The determination of peroxide value and acid value is not affected by pretreatment methods, ensuring more representative results. It addresses the challenges of difficult oil separation and extraction from oil-rich emulsified encapsulated sauces and solves significant issues encountered when using acid hydrolysis and alkaline hydrolysis methods to determine peroxide value and acid value. It enables the simultaneous monitoring of three physicochemical indicators (fat content, peroxide value, and acid value).

Abstract: A method includes providing a zeolite material including a plurality of active sites. The plurality of active sites are bound to a plurality of hydrogen ions. The method includes exchanging at least a portion of the plurality of hydrogen ions with a plurality of copper ions, thereby forming a first amount of Z2Cu active sites that include copper (Cu2+) ions bound to the zeolite material and a first amount of ZCuOH active sites bound to copper hydroxide ions bound to the zeolite material. The method includes heating the zeolite material to a heat treatment temperature for a predefined time period to transform the zeolite material into a heat treated zeolite material. The heat treated zeolite material includes a second amount of Z2Cu active sites greater than the first amount of Z2Cu active sites and a second amount of ZCuOH active sites less than the first amount of ZCuOH active sites.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: A stator structure is provided and includes a plurality of first lamination layers, a plurality of second lamination layers, two third lamination layers and two oil spraying rings. The second lamination layers are sandwiched in between the first lamination layers. The second lamination layer located in the middle of the stator structure is sandwiched in between the two third lamination layers. The two oil spraying rings are connected to two first lamination layers located at outermost sides. Another stator structure is provided and includes a plurality of first lamination layers, a second lamination layer and two oil spraying rings. The second lamination layer is sandwiched in between two first lamination layers. The two oil spraying rings are connected to two first lamination layers located at outermost sides. By means of the arrangement of the aforesaid stator structure, the invention can effectively improve heat dissipating effect for oil cooling.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.

Abstract: A shielding cover and a display device are provided. The shielding cover includes: a shielding cover body; and a shielding cover accessory fixedly connected to the shielding cover body. The shielding cover accessory includes: an accessory bottom including a flat bottom; a connecting arm through which the shielding cover accessory is connected to the shielding cover body; and a positioning arm. The connecting arm and the positioning arm are connected to two opposite ends of the accessory bottom, and protrude in opposite directions from the accessory bottom. The shielding cover accessory further includes a plurality of card slots arranged at positions of the flat bottom close to the positioning arm, each card slot penetrates the flat bottom in a direction perpendicular to the flat bottom, and the plurality of card slots are arranged at intervals in a direction parallel to an extending direction of the positioning arm.

Abstract: A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.

Abstract: A method for training a three-dimensional face reconstruction model includes inputting an acquired sample face image into a three-dimensional face reconstruction model to obtain a coordinate transformation parameter and a face parameter of the sample face image; determining the three-dimensional stylized face image of the sample face image according to the face parameter of the sample face image and the acquired stylized face map of the sample face image; transforming the three-dimensional stylized face image of the sample face image into a camera coordinate system based on the coordinate transformation parameter, and rendering the transformed three-dimensional stylized face image to obtain a rendered map; and training the three-dimensional face reconstruction model according to the rendered map and the stylized face map of the sample face image.

Abstract: A method for forming a three-dimensional (3D) memory device is provided. A dielectric stack including dielectric/sacrificial layer pairs are formed on a doped semiconductor layer. A channel structure extending vertically through the dielectric stack is formed. A slit extending vertically in the dielectric stack is formed to expose the doped semiconductor layer. A bottommost sacrificial layer in the dielectric/sacrificial layer pairs is removed to form a first cavity in the dielectric stack. A source select gate line is formed in the first cavity in the dielectric stack. Sacrificial layers in the dielectric/sacrificial layer pairs are removed to form second cavities in the dielectric stack. Word lines are formed in the second cavities in the dielectric stack.

Abstract: A bi-directional and multi-channel optical module incudes a casing, an optical transmitter assembly, an optical receiver assembly and an optical fiber adaptor. The optical transmitter assembly is disposed in an accommodation space of the casing. The optical transmitter assembly includes a plurality of light emission units and a wavelength division multiplexer disposed corresponding to the plurality of light emission units. The optical receiver assembly is disposed in the accommodation space. The optical receiver assembly includes a plurality of light receiving units and a wavelength demultiplexer disposed corresponding to the plurality of light receiving units. The optical fiber adaptor is disposed on the casing.

Abstract: A semiconductor device includes a first structure having a first semiconductor layer and a first transistor of a memory cell, a second structure having a second semiconductor layer, a capacitor structure of the memory cell, and a third dielectric stack formed therein, and bonding structures formed between the first structure and the second structure. The bonding structures are configured to couple the first transistor to the capacitor structure to form the memory cell.

Abstract: The present disclosure provides a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a semiconductor layer, a first stack structure, a second stack structure, a gate line isolation structure, and a first dielectric layer. The first stack structure includes a plurality of first insulating layers and a plurality of gate line layers disposed alternatively. The second stack structure is disposed on a side of the first stack structure away from the semiconductor layer and includes a select gate line layer. The gate line isolation structure penetrates through the first stack structure and the second stack structure in a direction perpendicular to the semiconductor layer. The first dielectric layer is disposed on a side of the second stack structure away from the semiconductor layer, contacts the gate line isolation structure, and covers at least a part of a surface of the gate line isolation structure away from the semiconductor layer.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stack structure including conductor layers and dielectric layers stacked alternately along a first direction. The semiconductor device may include at least one semiconductor structure penetrating through the stack structure. The semiconductor structure may include a capacitor structure, a first transistor structure, and a second transistor structure extending in the stack structure along the first direction. The second transistor structure, the first transistor structure, and the capacitor structure in a same semiconductor structure may be arranged and connected sequentially along the first direction.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure including a core region and a staircase region, a channel structure extending through the stack structure in the core region, and a first support structure extending through the stack structure in the staircase region. The first support structure includes a first portion extending along a first direction and a second portion protruding from the first portion along a second direction perpendicular to the first direction. The first support structure is located between two blocks of the 3D memory device.

Abstract: A semiconductor structure and a manufacturing method thereof, and a memory system are provided. The semiconductor structure may include a stack structure including a first region, a second region and a boundary region between the first region and the second region. The stack structure includes gate layers and insulation layers stacked alternately, and the gate layers include a first gate layer and a plurality of second gate layers on a side of the first gate layer. A first contact structure in the boundary region extends and connects to the first gate layer. A plurality of second contact structures in the second region extend and connect to the second gate layers of different layers respectively. A size of the first contact structure perpendicular to a stacking direction of the stack structure is different from sizes of the second contact structures perpendicular to the stacking direction.