Abstract: Some embodiments provide a method for monitoring a first service that executes in a Pod on a node of a Kubernetes deployment. At a second service executing on the node, the method monitors a storage of the node that stores core dump files to detect when a core dump file pertaining to the first service is written to the storage. Upon detection of the core dump file being written to the storage, the method automatically (i) generates an image of the first service based on data in the core dump file and (ii) instantiates a new container on the node to analyze the generated image in order to debug the first service.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device may also include a plurality of landing structures each disposed on a respective conductive layer at a respective stair. Each of the landing structures comprises a first layer of a first material and a second layer of a second material. The first layer is over the second layer. The second material is different from the first material.

Abstract: A method for extracting oils from sauces while simultaneously determining fat content, peroxide value, and acid value is disclosed. The method is simple to operate and requires uncomplicated equipment. It features a short testing cycle and high efficiency, and suitable for the extraction of oils from oil-rich emulsified encapsulated sauces (such as salad dressings) with high extraction rates. The determination of peroxide value and acid value is not affected by pretreatment methods, ensuring more representative results. It addresses the challenges of difficult oil separation and extraction from oil-rich emulsified encapsulated sauces and solves significant issues encountered when using acid hydrolysis and alkaline hydrolysis methods to determine peroxide value and acid value. It enables the simultaneous monitoring of three physicochemical indicators (fat content, peroxide value, and acid value).

Abstract: Provided is a kit for calibration of an isothermal polymerase chain reaction (PCR) analyzer and use thereof. The kit includes a standard substance, an amplification primer set, a reaction buffer, a polymerase, a dye, and a negative control. The standard substance is a DNA plasmid with a gradient concentration of 100 copies/?L to 106 copies/?L; the amplification primer set has nucleotide sequences shown in SEQ ID NO: 1 to SEQ ID NO: 6; the polymerase is a Bst DNA polymerase; and the dye is a loop-mediated isothermal amplification (LAMP) fluorescent dye (with excitation: 485 nm, emission: 498 nm, and a detection channel of SYBR® Green I or a FAM channel). The kit and a technology for calibration of an isothermal PCR instrument meet calibration demands of the isothermal PCR instrument and fill a technical gap.

Abstract: According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stacked layer and a top select gate layer located on the stacked layer. The semiconductor device may include a gate-line structure extending through the top select gate layer and the stacked layer. A portion of the gate-line structure that extends through the top select gate layer may be a first isolation structure, and the first isolation structure may include a contact layer in contact with the top select gate layer. The semiconductor device may include a channel structure extending through the stacked layer and a first dielectric layer located on the top select gate layer, where the first dielectric layer and the contact layer comprise different insulating materials. The semiconductor device may include a channel local contact extending through the first dielectric layer and corresponding to the channel structure.

Abstract: A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The drain select gate line includes a first dielectric layer in contact with the channel structure, and a first polysilicon layer in contact with the first dielectric layer.

Abstract: The present disclosure provides a three-dimensional (3D) memory. The 3D memory may include a stack structure including gate layers and dielectric layers disposed alternately. The stack structure may include a step structure including a plurality of staircase structures disposed in a first direction and having different heights in a second direction. The 3D memory may include a plurality of first stops disposed in the first direction and located on the plurality of steps of at least one of the staircase structures, with each of the plurality of first stops disposed on the corresponding step of the plurality of steps. The 3D memory may include a protection layer covering the step structure and the first stops. The 3D memory may include a plurality of contact posts each extending through the protection layer and the first stop and being connected with the gate layer in the step corresponding to the first stop.

Abstract: According to one aspect of the present disclosure, a three-dimensional memory is provided. The three-dimensional memory may include a stack structure comprising a gate layer and a dielectric layer disposed alternately and comprising a plurality of steps. The three-dimensional memory may include an etch stop layer disposed on the plurality of steps. The three-dimensional memory may include a protective layer covering the stack structure and the etch stop layer. The three-dimensional memory may include a plurality of connection pillars. Each of the connection pillars penetrates through the protective layer and the etch stop layer on a corresponding step and is connected with the gate layer of the corresponding step.

Abstract: Provided are an essential oil composition and a preparation method thereof. The essential oil composition includes a eutectic composition and an essential oil; the eutectic composition includes a hydrogen-bond donor and a hydrogen-bond acceptor; the hydrogen-bond donor is geranic acid or derivatives of the geranic acid; the hydrogen-bond acceptor is choline or derivatives or hydrates of the choline; a mass ratio of the hydrogen-bond donor to the hydrogen-bond acceptor is 1-10:1-10.

Abstract: In a method and system for treating a catalytic cracking gasoline, a catalytic cracking process, or a plant employs a fluidized reactor to carry out hydrodealkylation treatment on a catalytic cracking oil gas or catalytic cracking gasoline, so that heavy aromatics present therein can be efficiently converted into light olefins and light aromatics. The method and system can improve the yield of light olefins, allow a long-period stable operation, relieve the contradiction between supply and demand of light aromatics, and solve the problem of high content of heavy aromatics that have low value and are difficult to be utilized in aromatics present in oil gas from catalytic cracking units.

Abstract: Systems, apparatuses, and methods include predicting a sulfur exposure of one or more copper-zeolite catalysts deployed in an exhaust aftertreatment system; comparing the predicted sulfur exposure to a predefined sulfur exposure threshold; and responsive to the determination, heating the exhaust aftertreatment catalyst to a predefined heat treatment temperature for a predefined time period to desulfate the one or more copper-zeolite catalysts.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

Abstract: A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.

Abstract: Examples of the present disclosure disclose a fabrication method of a semiconductor device, a semiconductor device and a memory system. The method includes: providing a stack structure including a device region and a connection region arranged in a first direction, the stack structure including an interlayer insulating layer and a composite material layer alternatively stacked in a second direction, the composite material layer including a bit line in the connection region, and the second direction intersecting the first direction; forming a contact hole in the connection region, the contact hole extending to the bit line from a first side of the stack structure in the second direction; and forming a contact structure connected with bit line in the contact hole.

Abstract: A method and a system for large-scale traffic generation based on programmable network technology, which are used for the research on network operation and maintenance and defense of attacks such as DDOS. According to the method, the required large-scale traffic is generated as required through the coordination of servers and programmable switches. The method specifically comprises the steps of designing a series of primitives which are based on intentions and are irrelevant to underlying architecture details, and reducing the description difficulty of generating large-scale traffic intentions; completing required configurations on the switch and the server by the designed cooperation mechanism of the server and programmable switch according to intentions expressed by different types of primitives, and achieving large-scale traffic generation by coordinating and utilizing server and switch resources.

Abstract: A micro-colorimetric sensor for sensing target chemicals using edge tracking includes a substrate. A plurality of parallel linear channels of porous media is entrenched into the substrate and each linear channel includes a sensing material adapted to sense one of several specific target chemicals in air. The plurality of parallel linear channels is separated by barrier material from the adjacent parallel linear channel where the barrier material blocks diffusion of chemicals from one linear channel to another. A plate is affixed over the substrate top to cover the plurality of parallel linear channels. An air sample is diffused along the micro-colorimetric sensor and color images are captured. An intensity profile is derived from the plurality of color images to determine a maximum and a minimum intensity value along the sensor. A plurality of positions along the sensor is tracked to determine an edge position.

Abstract: A memory device includes a semiconductor substrate, a first continuous floating gate structure, a dielectric layer, and a control gate electrode. The semiconductor substrate has a first active region. The first continuous floating gate structure is over the first active region of the semiconductor substrate, wherein the first continuous floating gate structure has first and second inner sidewalls facing each other. The dielectric layer has a first portion extending along the first inner sidewall of the first continuous floating gate structure and a second portion extending along the second inner sidewall of the first continuous floating gate structure. The control gate electrode is over the dielectric layer. The control gate electrode is in contact with the first and second portions of the dielectric layer.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure containing a core region and a staircase region, a channel structure extending through the stack structure in the core region, and a first support structure extending through the stack structure in the staircase region. The first support structure includes a first portion extending along a first direction and a second portion protruding from the first portion along a second direction perpendicular to the first direction.