Abstract: A memory device includes a semiconductor substrate, a first continuous floating gate structure, a dielectric layer, and a control gate electrode. The semiconductor substrate has a first active region. The first continuous floating gate structure is over the first active region of the semiconductor substrate, wherein the first continuous floating gate structure has first and second inner sidewalls facing each other. The dielectric layer has a first portion extending along the first inner sidewall of the first continuous floating gate structure and a second portion extending along the second inner sidewall of the first continuous floating gate structure. The control gate electrode is over the dielectric layer. The control gate electrode is in contact with the first and second portions of the dielectric layer.

Abstract: Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.

Abstract: A tunable-liquid-crystal-grating-based holographic true 3D display system comprises a laser, a filter, a beam expander, a semi-transparent semi-reflective mirror, a spatial light modulator, a lens I, a diaphragm, a tunable liquid crystal grating, a polaroid, a signal controller, a lens II and a receiving screen. The laser, the filter and the beam expander are used for generating collimated incident light. The spatial light modulator is loaded with a hologram of a 3D object. The diaphragm is positioned behind the lens I for eliminating a high-order diffracted light in the holographic true 3D display. The tunable liquid crystal grating is located on the back focal plane of the lens I and on the front focal plane of the lens II, and the signal controller is used for synchronously controlling the voltage of the tunable liquid crystal grating and the generation and loading of the hologram.

Abstract: The present disclosure provides a displacement detection circuit of a maglev rotor system and a displacement self-sensing system thereof.

Abstract: Systems and methods include connecting to and authenticating a plurality of user devices; utilizing a plurality of RESTful (Representational State Transfer web service) endpoints to communicate with the plurality of user devices; providing any of policy and configuration to the plurality of user devices utilizing version number via a RESTful endpoint; caching the any of policy and configuration for each device of the plurality of user devices; and receiving metrics based on measurements at the plurality of user devices according to corresponding policy and configuration, via a RESTful endpoint.

Abstract: A method for training a three-dimensional face reconstruction model includes inputting an acquired sample face image into a three-dimensional face reconstruction model to obtain a coordinate transformation parameter and a face parameter of the sample face image; determining the three-dimensional stylized face image of the sample face image according to the face parameter of the sample face image and the acquired stylized face map of the sample face image; transforming the three-dimensional stylized face image of the sample face image into a camera coordinate system based on the coordinate transformation parameter, and rendering the transformed three-dimensional stylized face image to obtain a rendered map; and training the three-dimensional face reconstruction model according to the rendered map and the stylized face map of the sample face image.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack structure and a contact structure. The stack structure comprises interleaved gate layers and insulating layers. The contact structure comprises a conductive structure and one or more insulating structures. The conductive structure can extend through the stack structure and form a conductive connection with one of the gate layers. The one or more insulating structures surround the conductive structure and electrically isolate the conductive structure from remaining ones of the gate layers. The one or more insulating structures further include one or more first insulating structures. Each of the one or more first insulating structures is disposed between an adjacent pair of the insulating layers, and the one or more first insulating structures are disposed on a first side of the one of the gate layers.

Abstract: A three-dimensional (3D) memory device includes a plurality of memory planes and a separation block. Each memory plane includes a plurality of memory blocks. Each memory block includes a memory stack including interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending through the memory stack. The separation block extending laterally to separate each two adjacent memory planes. Each separation block includes a dielectric stack including interleaved second dielectric layers and the first dielectric layers. The first dielectric layers extend across the memory blocks and the separation block, and the second dielectric layers separate the conductive layers of two adjacent memory blocks.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device also includes a plurality of landing structures each over a respective conductive layer at a respective stair. Each of the landing structures includes a first layer having a first material and a second layer having a second material, the first layer being over the second layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a stack structure, and a slit structure extending. The stack structure includes interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure. Each one of the conductive layers has a thickened portion in the staircase structure. The thickened portion extends along a first direction. The slit structure extends through the stack structure and along a second direction perpendicular to the first direction, such that the slit structure cuts off at least one, but not all, of the thickened portions of the conductive layers.

Abstract: Techniques for video manipulation using a product card within a short-form video environment are disclosed. Display is accomplished using a video stream interface that can be executed on an electronic device associated with a user. The video stream, such as a short-form video or livestream video, can include one or more products. The display shows product cards associated with the products within the video. The product cards originate from a repository, a third-party website, or some other source. The product information includes text, video, and/or audio content. The user is provided an option to purchase one or more of the products presented within the video by selecting the product card. The viewer selects product cards displayed in front of the video to learn more about the products and/or purchase the products.

Abstract: Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.

Abstract: A computer device includes a processor configured to simulate a virtual environment based on a set of virtual environment parameters, and perform ray tracing to render a view of the simulated virtual environment. The ray tracing includes generating a plurality of rays for one or more pixels of the rendered view of the simulated virtual environment. The processor is further configured to determine sub-pixel data for each of the plurality of rays based on intersections between the plurality of rays and the simulated virtual environment, and store the determined sub-pixel data for each of the plurality of rays in an image file.

Abstract: A neuron device including: an antiferromagnetic pinning layer, a first ferromagnetic layer and a spin orbit coupling layer formed on a substrate in sequence; a free layer formed on the spin orbit coupling layer and moving a magnetic domain wall according to a spin orbit torque; a tunneling layer formed on the free layer; a left pinning layer and a right pinning layer formed on two sides of the free layer and having opposite magnetization directions; and a reference layer formed on the tunneling layer; wherein the free layer, the tunneling layer and the reference layer constitute a magnetic tunnel junction, and the magnetic tunnel junction is configured to read neuronal signals. Also provided is a method for preparing a neuron device based on a spin orbit torque.

Abstract: A composite hydrogel sponge and its preparation method and application, and a solar desalination device are provided. The composite hydrogel sponge includes a water supply layer and an evaporation layer disposed on the water supply layer. A material of the water supply layer is polyacrylamide hydrogel, and a material of the evaporation layer is polyacrylamide/graphene composite hydrogel. The polyacrylamide/graphene composite hydrogel includes the polyacrylamide hydrogel and the graphene dispersed in the polyacrylamide hydrogel. The composite hydrogel sponge has a special porous structure of the sponge, which is beneficial to the rapid transmission and supply of water; meanwhile, the graphene on the surface of the evaporation layer can fully receive solar energy to achieve higher photo-thermal conversion efficiency.

Abstract: A memory device is provided. The memory device includes a semiconductor substrate, a tunneling layer, a floating gate electrode, a dielectric layer, and a control gate electrode. The semiconductor substrate has an active region. The tunneling layer is over the active region of the semiconductor substrate. The floating gate electrode is over the tunneling layer. The floating gate electrode has a first portion and a second portion electrically connected to the first portion. The dielectric layer is over the floating gate electrode. The control gate electrode is over the dielectric layer. The control gate electrode has a first portion interposed between the first and second portions of the floating gate electrode.

Abstract: An array substrate and a liquid crystal display panel thereof. The array substrate includes a substrate having a plurality of pixel regions arranged in an array. Each of the pixel regions (120a) includes: a first electrode, a second electrode, an insulation protrusion, and a reflection electrode. An electric field is fit to form between the second electrode and the first electrode, and an electric field is also fit to form between the reflection electrode and the second electrode. The second electrode includes a slit electrode, which includes a plurality of slit portions and a plurality of electrode portions each arranged between adjacent slit portions. The electrode portion at least includes a first strip-shaped portion and a second strip-shaped portion. An extension direction of the first strip-shaped portion intersects with that of the second strip-shaped portion, and the first strip and second strip-shaped portions of each electrode portion are connected at a corresponding bending portion.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure comprises a memory cell comprising: a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact coupled to a word line and surrounding a first portion of the insulating layer, and multiple plate line contact segments coupled to multiple plate lines respectively and surrounding a second portion of the insulating layer. The memory structure further comprises a bit line contact coupled to a bit line and coupled to a first end of the cylindrical body, a source line contact coupled to a source line, and a source cap coupled between the source line contact and a second end of the cylindrical body to increase a distance between the source line contact and the plate line contact segments.