Patents by Inventor Di Wang

Di Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12144175
    Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first stack of layers including a source connection layer and a second stack of layers including gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatively upon the first stack of layers. Further, the semiconductor device includes channel structures that are formed along the first direction in the first stack of layers and the second stack of layers, and a gate line cut structure having a trench that cuts through the first stack of layers and the second stack of layers. The trench is filled with at least an insulating layer. The semiconductor device includes a support structure having a first portion that is disposed at a side of the gate line cut structure and extended from the side of the gate line cut structure and underneath the second stack of layers.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: November 12, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Di Wang, Rui Su, Zhongwang Sun, Zhiliang Xia, Wenxi Zhou
  • Publication number: 20240335495
    Abstract: Provided are an essential oil composition and a preparation method thereof. The essential oil composition includes a eutectic composition and an essential oil; the eutectic composition includes a hydrogen-bond donor and a hydrogen-bond acceptor; the hydrogen-bond donor is geranic acid or derivatives of the geranic acid; the hydrogen-bond acceptor is choline or derivatives or hydrates of the choline; a mass ratio of the hydrogen-bond donor to the hydrogen-bond acceptor is 1-10:1-10.
    Type: Application
    Filed: March 13, 2024
    Publication date: October 10, 2024
    Inventors: ZHENFENG WU, WEI HE, DI WANG, MING YANG, NA WAN
  • Publication number: 20240338830
    Abstract: In some examples, systems and methods for user-assisted object detection are provided. For example, a method includes: receiving a first image frame in a sequence of image frames, performing object tracking using an object tracker to identify a first object of interest and a second object of interest in the first image frame based at least in part on one or more first templates associated with the first object of interest, one or more second templates associated with the second object of interest, and a spatial relationship between the first object of interest and the second object of interest, outputting a first indicator associated with a first image portion corresponding to the identified first object of interest, and outputting a second indicator associated with a second image portion corresponding to the identified second object of interest.
    Type: Application
    Filed: April 3, 2024
    Publication date: October 10, 2024
    Inventors: Aleksandr Patsekin, Ben Radford, Daniel Marasco, Dimitrios Lymperopoulos, Keun Jae Kim, Michel Goraczko, Prasanna Srikhanta, Rodney LaLonde, Tong Shen, Xin Li, Yue Wu, Cameron Derwin, Di Wang
  • Publication number: 20240334838
    Abstract: The present disclosure provides an SOT-MRAM memory cell, including: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor, a drain of which is connected to the orbital Hall effect layer; and a second transistor, a drain of which is connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.
    Type: Application
    Filed: March 2, 2022
    Publication date: October 3, 2024
    Inventors: Guozhong Xing, Long Liu, Xuefeng Zhao, Di Wang, Huai Lin, Hao Zhang, Ziwei Wang
  • Publication number: 20240321777
    Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is provided. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. A plurality of channel structures are formed in a first region of the stack structure. A staircase structure is formed in a second region of the stack structure. A first portion of each of the second dielectric layers is replaced with a conductive layer, such that the conductive layer is partially separated between the staircase structure and the plurality of channel structures by a remainder of the second dielectric layer.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Inventors: Zhong Zhang, Di Wang, Wenxi Zhou
  • Publication number: 20240313427
    Abstract: This application provides an antenna and a communication system. The antenna includes a front mounting surface, a side mounting surface, a front radiating element array, and a side radiating element array. The front radiating element array is mounted on the front mounting surface, and the side radiating element array is mounted on the side mounting surface. An included angle on a side away from the front radiating element array is a first included angle, and the first included angle is less than 180°. One end of a circuit module is connected to an antenna port connected to the front radiating element array and an antenna port connected to the side radiating element array, and another end of the circuit module is configured to connect to radio frequency ports.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Inventors: Bojie Li, Zhi Gong, Weihong Xiao, Guanxi Zhang, Di Wang, Xianghua Li
  • Publication number: 20240312027
    Abstract: In some examples, systems and methods for object tracking are provided. For example, a method includes: receiving an image frame in a sequence of image frames; identifying an object of interest in the image frame using a single-object tracker (SOT) based upon one or more templates associated with the object of interest in a template repository; generating a SOT output based on the identified object of interest; and detecting one or more objects in the image frame using a multiple-object tracker (MOT). In some examples, the MOT including a machine-learning model. In some examples, the method further includes conducting a matching between the SOT output and each detected object of the one or more detected objects to generate a match result; and generating a tracker output based at least in part on the SOT output, the one or more detected objects, and the match result.
    Type: Application
    Filed: February 20, 2024
    Publication date: September 19, 2024
    Inventors: Aleksandr Patsekin, Ben Radford, Cameron Derwin, Daniel Marasco, Di Wang, Dimitrios Lymperopoulos, Elliot Kang, Keun Jae Kim, Matthew Betten, Matthew Fedderly, Michel Goraczko, Peng Lei, Prasanna Srikhanta, Rodney LaLonde, Steven Fackler, Tong Shen, Xin Li, Yue Wu
  • Patent number: 12094767
    Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: September 17, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ling Xu, Di Wang, Zhong Zhang, Wenxi Zhou
  • Publication number: 20240303831
    Abstract: In some examples, systems and methods for user-assisted object detection are provided. For example, a method includes: receiving a first image frame of a sequence of image frames, performing object detection using an object tracker to identify an object of interest in the first image frame, based upon one or more templates associated with the object of interest in a template repository, outputting a first indicator associated with a first image portion corresponding to the identified object of interest, and receiving a user input associated with the object of interest. In some examples, the user input indicates an identified image portion in the image frame. In some examples, the method further includes generating a retargeted template, based at least in part on the identified image portion, and determining a second image portion associated with the object of interest in a second image frame of the sequence of image frames using the object tracker, based at least in part on the retargeted template.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 12, 2024
    Inventors: Aleksandr Patsekin, Ben Radford, Cameron Derwin, Daniel Marasco, Di Wang, Dimitrios Lymperopoulos, Elliot Kang, Keun Jae Kim, Matthew Betten, Matthew Fedderly, Michel Goraczko, Peng Lei, Prasanna Srikhanta, Rodney LaLonde, Steven Fackler, Tong Shen, Xin Li, Yue Wu
  • Publication number: 20240296671
    Abstract: In some examples, systems and methods for user-assisted object detection are provided. For example, a method includes: receiving an input image, and performing object detection by a software detector to identify a set of detected objects. The software detector includes a machine-learning model. The method further includes outputting one or more indicators of the set of detected objects. Each detected object in the set of detected objects is associated with a confidence level. The method further includes receiving a user input; identifying a template including an image portion associated with the user input; determining a similarity metric between the template and an object in the set of detected objects; modifying a confidence level of the object based at least in part on the determined similarity metric; and generating an output including an indicator of the object based at least in part on the modified confidence level.
    Type: Application
    Filed: February 19, 2024
    Publication date: September 5, 2024
    Inventors: Aleksandr Patsekin, Ben Radford, Cameron Derwin, Daniel Marasco, Di Wang, Dimitrios Lymperopoulos, Keun Jae Kim, Michel Goraczko, Peng Lei, Prasanna Srikhanta, Rodney LaLonde, Tong Shen, Xin Li, Yue Wu
  • Publication number: 20240298443
    Abstract: A method of memory device fabrication includes, providing a structure that includes first layers including word lines interleaved respectively with first dielectric layers, second layers including second dielectric layers interleaved respectively with the first dielectric layers, wherein the second layers are adjacent to the first layers, forming vertical recesses each of which extend to a surface of a respective one of the second dielectric layers in a first direction through the second layers, etching a respective lateral recess to expose a surface of a respective one of the word lines, and filling each respective lateral recess with at least one conductive material, such that the at least one conductive material in the respective lateral recess is in contact with the respective one of the word lines through the exposed surface.
    Type: Application
    Filed: April 5, 2023
    Publication date: September 5, 2024
    Inventors: Zhong Zhang, Di Wang, Wenxi Zhou
  • Publication number: 20240298150
    Abstract: Disclosed are a 5th generation (5G) message processing method, a 5G message center, a terminal device, and a storage medium. The 5th Generation (5G) message processing method may include: determining a first node and a second node from all nodes which are to receive a 5G message, and generating a first list according to node information of the first node, wherein the first node and the second node belong to the 5G message center; sending, to the first node, a group-sending file corresponding to the 5G message; and delivering, to the second node, a notification message comprising the first list and a group-sending notification, such that the second node acquires the group-sending file from at least one first node in the first list according to the group-sending notification.
    Type: Application
    Filed: October 9, 2021
    Publication date: September 5, 2024
    Inventors: Di WANG, Cuiping YANG, Dong XIE
  • Publication number: 20240280898
    Abstract: This application provides an organic mixed metal-oxygen cluster compound, and a chemical general formula thereof is as follows: (M1)a(M2)b(M3)cOg(L1)x(L2)y(L3)z, where M1 is selected from at least one of Ti, Zr, and Hf; M2 is selected from at least one of Bi, Te, Sn, Pt, Ag, and Au; M3 is selected from one of Fe, Ni, Co, and Cu; L1, L2, and L3 are respectively selected from organic ligands that directly coordinate with a metal and include one of O, S, Se, N, and P that serves as a ligating atom; a, b, g, x, y, and z are all natural numbers greater than or equal to 1; and c is a natural number greater than or equal to 0. This application further provides a patterning material including the organic mixed metal-oxygen cluster compound, a semiconductor device including the patterning material, a terminal, and a substrate surface patterning method.
    Type: Application
    Filed: April 26, 2024
    Publication date: August 22, 2024
    Inventors: Lei ZHANG, Xiaofeng YI, Di WANG, Qingrong DING, Yu ZHANG
  • Publication number: 20240282376
    Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 22, 2024
    Inventors: DongXue ZHAO, Tao YANG, Yuancheng YANG, Lei LIU, Di WANG, Kun ZHANG, Wenxi ZHOU, Zhiliang XIA, Zongliang HUO
  • Publication number: 20240274535
    Abstract: In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure. The staircase structure includes a plurality of stairs extending along a first lateral direction. The plurality of stairs include a stair including a conductor portion on a top surface of the stair. The conduction portion is connected to the memory array structure. Widths of conductor portions are different in a second lateral direction perpendicular to the first lateral direction.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Di WANG, Wenxi ZHOU, Zhiliang XIA, Zhong ZHANG
  • Patent number: 12054680
    Abstract: A method for producing light aromatics, includes the steps of: i) contacting a feedstock comprising heavy aromatic(s) with a catalyst in a fluidized reactor for aromatics lightening reaction in the presence of hydrogen to obtain a product rich in C6-C8 light aromatic(s) and a spent catalyst, wherein the heavy aromatic is one or more selected from C9+ aromatics; ii) separating the resulted product rich in C6-C8 light aromatic(s) to obtain hydrogen, a non-aromatic component, C6-C8 light aromatic(s) and a C9+ aromatic component; and iii) recycling at least a part of the C9+ aromatic component to the fluidized reactor. The method has strong adaptability to feedstocks and high flexibility in operation and allows a long-period stable operation. The method can produce high-value light aromatics from heavy aromatics that are difficult to be treated and utilized.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 6, 2024
    Assignees: CHINA PETROLEUM & CHEMICAL CORPORATION, RESEARCH INSTITUTE OF PETROLEUM PROCESSING, SINOPEC
    Inventors: Di Wang, Xiaoli Wei, Jianhong Gong, Jingchuan Yu, Jiushun Zhang
  • Patent number: 12053746
    Abstract: The present application provides a high-gravity device for generating nano/micron bubble and a reaction system. In the device, the liquid phase is continuous phase and the gas phase is dispersed phase. A gas enters the interior of the device from a hollow shaft, and the gas is subjected to primary shearing under a shearing effect of aerating micropores to form bubbles; then, the bubbles rapidly disengage from the surface of a rotating shaft under the effect of the rotating shaft rotating at a high speed, and are subjected to secondary shearing under the high-gravity environment with the strong shearing force formed by the rotating shaft to form nano/micron bubbles. The device has the advantages of fastness, stability, and small average particle size. The average particle size of the formed nano/micron bubbles is between 800 nanometers and 50 microns, and the average particle size of the bubbles can be regulated in a range by adjusting the rotating speed of the rotating shaft.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: August 6, 2024
    Assignee: BEIJING UNIVERSITY OF CHEMICAL TECHNOLOGY
    Inventors: Yong Luo, Di Wang, Guangwen Chu, Yachao Liu, Zhihao Li, Yong Cai, Haikui Zou, Baochang Sun, Jianfeng Chen
  • Publication number: 20240232592
    Abstract: Provided are a reconfigurable neuron device based on ion gate regulation and a method of preparing the same. The device includes: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer and a top electrode layer which are sequentially stacked from bottom to top. A left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions are provided on two opposite edges of a bottom end of the synthetic antiferromagnetic layer, and a magnetic tunnel junction configured to output a spike signal is further provided in a middle portion of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer and the top electrode layer constitute an ion gate, the ionic liquid layer includes a positive ion and a negative ion.
    Type: Application
    Filed: March 3, 2022
    Publication date: July 11, 2024
    Inventors: Xuefeng ZHAO, Guozhong XING, Di WANG, Ziwei WANG, Long LIU, Huai LIN, Hao ZHANG
  • Patent number: 12033957
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: July 9, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhong Zhang, Di Wang, Wenxi Zhou
  • Publication number: 20240224517
    Abstract: A method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths. A portion of the second dielectric layers in the second region that is closest to the opening is converted into a dielectric material different from the material of the second dielectric layers.
    Type: Application
    Filed: January 4, 2023
    Publication date: July 4, 2024
    Inventors: Yang Chen, Di Wang, Jingtao Xie, Qingfu Zhang, Zhiliang Xia, Zongliang Huo