Abstract: This disclosure is directed to methods for performing operations on a memory device. The memory device can include a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap. The method can include applying a first positive voltage bias to the bottom select gate and applying a second positive voltage bias to the word line. The method can also include applying a third positive voltage bias to the bit line after the word line reaches the second positive voltage bias. The method can further include applying a ground voltage to the word line and applying the ground voltage to the bit line.

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a pad-out structure disposed on the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal in contact with the first side of the first semiconductor layer and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; and a plate line extending in the second direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure are stacked over one another.

Abstract: The present disclosure relates to a nano-cubic polyanionic electrode material, a preparation method therefor, and use thereof. The electrode material of the present disclosure comprises NasV2(PO4); @M; where M is a block polymer containing disulfide bond; further, a nano-cubic NVP@M@PDA material can be formed by using coupling between PDA and NVP. The conductivity performance and cycle performance of the material obtained in the present disclosure are greatly improved, and the present disclosure well solves the problems associated with matching with a hard carbon negative electrode.

Abstract: Disclosed is a system platform for evaluation and research and development of vibration and noise reduction technology for rail transit, including a hemi-anechoic chamber, a run-through tunnel, a simulated track, and a reduced-scale train running on the simulated track. The run-through tunnel is enclosed by sound insulation and absorption boards. The side wall of the hemi-anechoic chamber is provided with a door opening; the exit of the run-through tunnel communicates with the door opening, and the entrance of the run-through tunnel is arranged at the end part, away from the hemi-anechoic chamber, of the run-through tunnel. The simulated track is continuously arranged into the hemi-anechoic chamber from the outside of the run-through tunnel via the entrance, the exit and the door opening.

Abstract: Please replace the following substitute abstract for the abstract currently on file: A method for preparing a water-soluble rutin powder includes: heating and mixing a plant polysaccharide substance, a filler, and water to obtain a wall material solution; adding an antioxidant and a rutin powder into the wall material solution at a first temperature, followed by emulsification and dispersion, pH adjustment, and high-pressure homogenization to obtain a rutin powder emulsion; and carrying out heating fusion of the rutin powder emulsion to obtain a water-soluble rutin powder. With the preparation method, a water-soluble rutin product is obtained through emulsification, high-pressure homogenization, ultra-high-temperature fusion, drying and other processes by using modified starch and a plant polysaccharide as a wall material and rutin as a core material.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure is sandwiched between the first semiconductor structure and the fourth semiconductor structure, and the fourth semiconductor is sandwiched between the second semiconductor structure and the third semiconductor structure.

Abstract: A memory device includes an array of memory cells disposed on a first side of a first semiconductor layer, and a peripheral circuit bonded to the array of memory cells. Each of the memory cells includes a semiconductor body extending in a first direction, a first terminal and a second terminal are formed at both ends of the semiconductor body; a word line extending in a second direction perpendicular to the first direction; plate lines extending in the second direction; and a first dielectric layer disposed between the semiconductor body and the word line and the plate line.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction.

Abstract: Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.

Abstract: A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.

Abstract: A memory device includes a semiconductor layer; a peripheral circuit disposed on the semiconductor layer; and an array of memory cells disposed aside the peripheral circuit on the semiconductor layer. Each of the memory cells includes a semiconductor body extending in a first direction, a first end of the semiconductor body is in contact with the semiconductor layer; a word line gate extending in a second direction perpendicular to the first direction; a plate line gate extending in the second direction; and a dielectric layer disposed between the semiconductor body and the word line gate and the plate line gate.

Abstract: Memory device and formation method are provided. The memory device includes a stack structure; and a plurality of gate line slit structures vertically extending through the stack structure to divide the stack structure into a plurality of stack portions. The plurality of GLS structures extend along a first direction in a lateral plane of the stack structure and are arranged along a second direction substantially perpendicular to the first direction. Each stack portion is between corresponding adjacent gate line slit structures. At least one edge stack portion, along the second direction of the plurality of stack portions at edge of the stack structure includes a configuration different from a non-edge stack portion of the plurality of stack portions along the second direction.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a second region, and word lines each extending from the first region into at least a portion of the second region. At least one word line pick-up structure includes multiple sections each electrically connected to a different word line.

Abstract: In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.

Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device comprises a first semiconductor structure including a core region, a spacer region, and a periphery region, and a second semiconductor structure including a second periphery circuit on a substrate. The first semiconductor structure comprises a memory stack on a semiconductor layer in the core region, a first periphery circuit on the semiconductor layer in the periphery region, and a spacer structure in the spacer region to separate the memory stack and the first periphery circuit. The second semiconductor structure is connected to the first semiconductor structure.

Abstract: The present disclosure relates to the field of energy materials, and discloses a NASICON-type fluorophosphate with a molecular formula Na3MxV2NyP3-yO12Fz. M is at least one of Li, Na, K, Ni, Fe, Ca, Ti, Cr, Zn, Ag, Mo, Mg and Mn. N is at least one of B, Si, Ge and As. 0?x?4, 0?y?3, 0?z?1, and x=y+z. In embodiments, by introducing M and N, and ionic synergy of M, N and fluorine, the formed NASICON-type fluorophosphate material has greatly improved conductivity, which is conducive to improve coulombic efficiency and high-rate performance of sodium-ion batteries. The present disclosure further discloses a cathode electrode plate and a sodium-ion battery. The cathode electrode plate includes the NASICON-type fluorophosphate.

Abstract: A method for preparing a carbon nano tube/polyacrylic acid hydrogel, a product and an application thereof are provided. The method includes: oxidizing a carbon nanotube into a carboxylated carbon nanotube, thereafter performing in-situ polymerization with acrylic acid, sodium hydroxide, ammonium persulfate, triethanolamine and N, N-methylenebisacrylamide to obtain a carbon nanotube/polyacrylic acid hydrogel. The hydrogel has a uniform porous structure, facilitating a rapid transmission and supply of water. The carbon nanotubes in the hydrogel are of an array structure, achieving a full absorption of solar energy to realize a high-efficiency photothermal conversion. The gel is attached to a sponge base to obtain a solar-powered carbon nano tube/polyacrylic acid hydrogel steam generator for the photothermal conversion. The steam generator is used for solar seawater desalination, but can improve evaporation rate and evaporation efficiency.

Abstract: An activation function generator based on a magnetic domain wall driven magnetic tunnel junction and a method for manufacturing the same are provided, including: a spin orbit coupling layer configured to generate a spin orbit torque; a ferromagnetic free layer formed on the spin orbit coupling layer and configured to provide a magnetic domain wall motion racetrack; a nonmagnetic barrier layer formed on the ferromagnetic free layer; a ferromagnetic reference layer formed on the nonmagnetic barrier layer; a top electrode formed on the ferromagnetic reference layer; antiferromagnetic pinning layers formed on two ends of the ferromagnetic free layer; a left electrode and a right electrode respectively formed at two positions on the antiferromagnetic pinning layers.

Abstract: The present disclosure discloses a method for inhibiting formation of a biofilm of bacteria. Specifically, the method may include treating the bacteria with an effective amount of a coumarin-chalcone compound. While inhibiting the formation of the biofilm of the bacteria, the effective amount of the coumarin-chalcone compound may reduce virulences of the bacteria and enhance a susceptibility of the bacteria to an antibiotic when applied in combination with the antibiotic. The present disclosure further discloses a composition including an effective amount of the coumarin-chalcone compound. The composition may be used to inhibit the formation of the biofilm of bacteria. The composition may also include an antibiotic, a minimal inhibitory concentration and a minimal biofilm eliminate concentration of which are reduced when the composition is used.