Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

Abstract: A system of cleaning a CMP pad used for removing copper from a substrate, the system comprising an abrasive cleaning pad, a cleaning solution delivery system that delivers a cleaning solution, an analyzing system that monitors the characteristics of the cleaning solution optically and chemically, and a carriage that allows the analyzing system to monitor the cleaning solution at a plurality of locations on the CMP pad. The use of the abrasive cleaning pad and the cleaning solution removes contaminants from the CMP pad, and the contaminants are dissolved in the cleaning solution. By measuring the concentration of contaminants in the cleaning solution, the condition of the CMP pad can be monitored. To measure the concentration of the contaminants, changes in the refractive index and absorption of light in the cleaning solution are measured, wherein the refractive index and absorption depend on the concentration of the contaminants.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch. The charge buildup along a top and a bottom of the sidewall may reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer may be formed to electrically short the upper and lower portions of the sidewall and eliminate the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and structures are described.

Abstract: A recovery system for platinum electrolytic baths operating at low current densities is disclosed. An oxidizing system is provided in a closed-loop recirculation system for platinum plating at low current densities. The oxidizing system reoxidizes Pt+2 ions, which are typically formed at low current densities, to Pt+4 ions by using oxidizers, for example peroxide. A sensor may be also provided to detect the relative concentration of [Pt+2] ions to [Pt+4] ions and to tailor the relative concentrations to a predetermined level.

Abstract: A method and apparatus for cleaning a web-based chemical-mechanical planarization (CMP) system. Specifically, a fluid spray bar is coupled to a frame assembly which may be mounted on a CMP system. The fluid spray bar will move along the frame assembly. As the fluid spray bar traverses the length of the frame assembly, a cleaning fluid is sprayed onto the web in order to clean the web between planarization cycles.

Abstract: Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

Abstract: Methods and apparatus for forming conductive interconnect layers useful in articles such as semiconductor chips, memory devices, semiconductor dies, circuit modules, and electronic systems. An electrochemical cell may be used in the reduction of oxides on a dual-purpose layer.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.

Abstract: A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer.

Abstract: A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a glazed portion of the pad, and then the conditioned pad portion may be used again for polishing. The conditioning device is preferably arranged to apply different conditioning treatments to different portions of the glazed pad. The conditioning device may have roller segments that rotate at different speeds. Alternatively, the device may have non-cylindrical rollers that provide different rotational speeds at the pad surface, or the device may apply different pressures at different portions of the pad. The device may be arranged to provide uniform conditioning across the width of the pad. The invention is applicable to methods of planarizing semiconductor wafers. The invention may be used to condition circular pads in addition to web-shaped pads.

Abstract: A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a glazed portion of the pad, and then the conditioned pad portion may be used again for polishing. The conditioning device is preferably arranged to apply different conditioning treatments to different portions of the glazed pad. The conditioning device may have roller segments that rotate at different speeds. Alternatively, the device may have non-cylindrical rollers that provide different rotational speeds at the pad surface, or the device may apply different pressures at different portions of the pad. The device may be arranged to provide uniform conditioning across the width of the pad. The invention is applicable to methods of planarizing semiconductor wafers. The invention may be used to condition circular pads in addition to web-shaped pads.

Abstract: A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer.

Abstract: The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method comprises forming a metal seed layer above a patterned layer of insulating material, the patterned layer of insulating material defining a plurality of field areas, deactivating at least a portion of the metal seed layer in areas where the metal seed layer is positioned above at least some of the field areas, and performing a deposition process to deposit a metal layer above the metal seed layer. In some embodiments, the metal may be comprised of copper, platinum, nickel, tantalum, tungsten, cobalt, etc. Portions of the metal seed layer may be deactivated by implanting ions into portions of the metal seed layer positioned above at least some of the field areas. The implanted ions may be comprised of nitrogen, carbon, silicon, hydrogen, etc.