Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad material is mixed with compressed gas to form a plurality of discrete elements that are distributed on a support material. At least a portion of the discrete elements are spaced apart from each other on the support material to form a textured surface for engaging a microelectronic substrate and removing material from the microelectronic substrate. The discrete elements can be uniformly or randomly distributed on the support material, and the discrete elements can be directly affixed to the support material or affixed to the support material with an adhesive.

Abstract: A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad material is mixed with compressed gas to form a plurality of discrete elements that are distributed on a support material. At least a portion of the discrete elements are spaced apart from each other on the support material to form a textured surface for engaging a microelectronic substrate and removing material from the microelectronic substrate. The discrete elements can be uniformly or randomly distributed on the support material, and the discrete elements can be directly affixed to the support material or affixed to the support material with an adhesive.

Abstract: A method of forming a conductive interconnect, preferably a copper interconnect, comprising a metal cap formed thereover. The metal cap is preferably comprises silver, gold, cobalt, nickel-tungsten, cobalt-tungsten, silver-tungsten or nickel. The conductive interconnect is fabricated by forming a substrate having a trench formed therein, forming a barrier layer over the substrate and within the trench, forming a conductive layer over the barrier layer and within the trench, planarizing the conductive layer to an upper surface of the barrier layer, recessing the conductive layer below an upper surface of the barrier layer, and forming a metal layer over the conductive layer via electroplating.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer.

Abstract: A method of forming a metal seed layer, preferably a copper layer, for subsequent electrochemical deposition. The metal seed layer is formed by the oxidation-reduction reaction of a metal salt with a reducing agent present in a layer on the substrate to be plated. Metal interconnects for semiconductor devices may be produced by the method, which has the advantage of forming the metal seed layer by a simple electrochemical plating process that may be combined with the plating of the interconnect itself as a single-bath operation.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a glazed portion of the pad, and then the conditioned pad portion may be used again for polishing. The conditioning device is preferably arranged to apply different conditioning treatments to different portions of the glazed pad. The conditioning device may have roller segments that rotate at different speeds. Alternatively, the device may have non-cylindrical rollers that provide different rotational speeds at the pad surface, or the device may apply different pressures at different portions of the pad. The device may be arranged to provide uniform conditioning across the width of the pad. The invention is applicable to methods of planarizing semiconductor wafers. The invention may be used to condition circular pads in addition to web-shaped pads.

Abstract: A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad material is mixed with compressed gas to form a plurality of discrete elements that are distributed on a support material. At least a portion of the discrete elements are spaced apart from each other on the support material to form a textured surface for engaging a microelectronic substrate and removing material from the microelectronic substrate. The discrete elements can be uniformly or randomly distributed on the support material, and the discrete elements can be directly affixed to the support material or affixed to the support material with an adhesive.

Abstract: A system of cleaning a CMP pad used for removing copper from a substrate, the system comprising an abrasive cleaning pad, a cleaning solution delivery system that delivers a cleaning solution, an analyzing system that monitors the characteristics of the cleaning solution optically and chemically, and a carriage that allows the analyzing system to monitor the cleaning solution at a plurality of locations on the CMP pad. The use of the abrasive cleaning pad and the cleaning solution removes contaminants from the CMP pad, and the contaminants are dissolved in the cleaning solution. By measuring the concentration of contaminants in the cleaning solution, the condition of the CMP pad can be monitored. To measure the concentration of the contaminants, changes in the refractive index and absorption of light in the cleaning solution are measured, wherein the refractive index and absorption depend on the concentration of the contaminants.

Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

Abstract: The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method includes forming a metal seed layer above a patterned layer of insulating material, the patterned layer of insulating material defining a plurality of field areas, deactivating at least a portion of the metal seed layer in areas where the metal seed layer is positioned above at least some of the field areas, and performing a deposition process to deposit a metal layer above the metal seed layer. In some embodiments, the metal may includes copper, platinum, nickel, tantalum, tungsten, cobalt, etc. Portions of the metal seed layer may be deactivated by implanting ions into portions of the metal seed layer positioned above at least some of the field areas. The implanted ions may includes nitrogen, carbon, silicon, hydrogen, etc.

Abstract: The present invention is generally directed to a method of reducing oxidation of metal structures using ion implantation, and a device constructed in accordance with the method. In one illustrative embodiment, the method comprises providing a semiconducting substrate having a first layer of insulating material formed thereabove, the first layer of insulating material having at least one conductive structure positioned therein, and performing an ion implant process to implant ions into at least the one conductive structure.

Abstract: The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method comprises forming a metal seed layer above a patterned layer of insulating material, the patterned layer of insulating material defining a plurality of field areas, deactivating at least a portion of the metal seed layer in areas where the metal seed layer is positioned above at least some of the field areas, and performing a deposition process to deposit a metal layer above the metal seed layer. In some embodiments, the metal may be comprised of copper, platinum, nickel, tantalum, tungsten, cobalt, etc. Portions of the metal seed layer may be deactivated by implanting ions into portions of the metal seed layer positioned above at least some of the field areas. The implanted ions may be comprised of nitrogen, carbon, silicon, hydrogen, etc.

Abstract: A planarization method includes providing an aluminum-containing surface and positioning it for contact with a fixed abrasive article in the presence of a composition preferably including a surfactant, a complexant, and an oxidant, wherein the solution has a pH of less than about 10.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: A method and apparatus for cleaning a web-based chemical-mechanical planarization (CMP) system. Specifically, a fluid spray bar is coupled to a frame assembly which may be mounted on a CMP system. The fluid spray bar will move along the frame assembly. As the fluid spray bar traverses the length of the frame assembly, a cleaning fluid is sprayed onto the web in order to clean the web between planarization cycles.