Patents by Inventor Dinesh Chopra

Dinesh Chopra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6703309
    Abstract: The present invention is generally directed to a method of reducing oxidation of metal structures using ion implantation, and a device constructed in accordance with the method. In one illustrative embodiment, the method comprises providing a semiconducting substrate having a first layer of insulating material formed thereabove, the first layer of insulating material having at least one conductive structure positioned therein, and performing an ion implant process to implant ions into at least the one conductive structure.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: March 9, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Dinesh Chopra
  • Publication number: 20040043582
    Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Inventor: Dinesh Chopra
  • Publication number: 20040043605
    Abstract: The present invention is generally directed to a method of reducing oxidation of metal structures using ion implantation, and a device constructed in accordance with the method. In one illustrative embodiment, the method comprises providing a semiconducting substrate having a first layer of insulating material formed thereabove, the first layer of insulating material having at least one conductive structure positioned therein, and performing an ion implant process to implant ions into at least the one conductive structure.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 4, 2004
    Inventor: Dinesh Chopra
  • Publication number: 20040023489
    Abstract: The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method comprises forming a metal seed layer above a patterned layer of insulating material, the patterned layer of insulating material defining a plurality of field areas, deactivating at least a portion of the metal seed layer in areas where the metal seed layer is positioned above at least some of the field areas, and performing a deposition process to deposit a metal layer above the metal seed layer. In some embodiments, the metal may be comprised of copper, platinum, nickel, tantalum, tungsten, cobalt, etc. Portions of the metal seed layer may be deactivated by implanting ions into portions of the metal seed layer positioned above at least some of the field areas. The implanted ions may be comprised of nitrogen, carbon, silicon, hydrogen, etc.
    Type: Application
    Filed: August 2, 2002
    Publication date: February 5, 2004
    Inventor: Dinesh Chopra
  • Publication number: 20040014318
    Abstract: A slurry for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The slurry, which is useful with a fixed-abrasive type polishing pad, is substantially abrasive-free and removes copper at a rate that is substantially the same as or faster than a rate at which it removes a material, such as tungsten, of the barrier layer. The slurry is formulated so as to oxidize copper at substantially the same rate as or at a faster rate than a material of the barrier layer is oxidized. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry or the oxidation energy of the barrier layer material in the slurry may be greater than that of copper. Systems and methods for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 22, 2004
    Inventors: Dinesh Chopra, Nishant Sinha
  • Publication number: 20040011554
    Abstract: A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material comprising the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may comprise annealing the first and second layer. An exemplary first metal comprises copper, and an exemplary second metal comprises aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 22, 2004
    Inventors: Dinesh Chopra, Fred Fishburn
  • Patent number: 6676484
    Abstract: The invention comprises copper chemical-mechanical polishing processes using fixed abrasive polishing pads, and copper layer chemical-mechanical polishing solutions specifically adapted for chemical-mechanical polishing with fixed abrasive pads. In one implementation, processes are described for pH's of 7.0 or greater. In one implementation, processes are described for pH's of 7.0 or less. In one implementation, a copper layer chemical-mechanical polishing solution specifically adapted for chemical-mechanical polishing with a fixed abrasive pad comprises a copper oxidizing component present at from about 1% to 15% by volume, a copper corrosion inhibitor present at from about 0.01% to 2% by weight, and a pH of less than or equal to 7.0. In one implementation, a copper layer chemical-mechanical polishing solution specifically adapted for chemical-mechanical polishing with a fixed abrasive pad comprises a copper oxidizing component present at from about 0.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: January 13, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Dinesh Chopra
  • Patent number: 6672949
    Abstract: A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a glazed portion of the pad, and then the conditioned pad portion may be used again for polishing. The conditioning device is preferably arranged to apply different conditioning treatments to different portions of the glazed pad. The conditioning device may have roller segments that rotate at different speeds. Alternatively, the device may have non-cylindrical rollers that provide different rotational speeds at the pad surface, or the device may apply different pressures at different portions of the pad. The device may be arranged to provide uniform conditioning across the width of the pad. The invention is applicable to methods of planarizing semiconductor wafers. The invention may be used to condition circular pads in addition to web-shaped pads.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: January 6, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Scott E. Moore
  • Patent number: 6672946
    Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: January 6, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Scott G. Meikle
  • Publication number: 20030228749
    Abstract: A method of forming a conductive interconnect, preferably a copper interconnect, comprising a metal cap formed thereover. The metal cap is preferably comprises silver, gold, cobalt, nickel-tungsten, cobalt-tungsten, silver-tungsten or nickel. The conductive interconnect is fabricated by forming a substrate having a trench formed therein, forming a barrier layer over the substrate and within the trench, forming a conductive layer over the barrier layer and within the trench, planarizing the conductive layer to an upper surface of the barrier layer, recessing the conductive layer below an upper surface of the barrier layer, and forming a metal layer over the conductive layer via electroplating.
    Type: Application
    Filed: May 15, 2003
    Publication date: December 11, 2003
    Inventors: Nishant Sinha, Dinesh Chopra
  • Publication number: 20030227091
    Abstract: A method of forming a conductive interconnect, preferably a copper interconnect, comprising a metal cap formed thereover. The metal cap is preferably comprises silver, gold, cobalt, nickel-tungsten, cobalt-tungsten, silver-tungsten or nickel. The conductive interconnect is fabricated by forming a substrate having a trench formed therein, forming a barrier layer over the substrate and within the trench, forming a conductive layer over the barrier layer and within the trench, planarizing the conductive layer to an upper surface of the barrier layer, recessing the conductive layer below an upper surface of the barrier layer, and forming a metal layer over the conductive layer via electroplating.
    Type: Application
    Filed: June 6, 2002
    Publication date: December 11, 2003
    Inventors: Nishant Sinha, Dinesh Chopra
  • Patent number: 6652364
    Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: November 25, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Scott G. Meikle
  • Patent number: 6652365
    Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: November 25, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Scott G. Meikle
  • Patent number: 6648736
    Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: November 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Scott G. Meikle
  • Patent number: 6638148
    Abstract: Apparatuses and methods for planarizing a mnicroelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: October 28, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Scott G. Meikle
  • Patent number: 6620032
    Abstract: Polishing pads, planarizing machines and methods for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays or other microelectronic substrate assemblies. One planarizing machine of the invention is a web-format machine having a planarizing table to support a portion of the polishing pad in a planarizing zone, at least one roller to hold another portion of the polishing pad, and a carrier assembly for handling a microelectronic substrate assembly. A web-format polishing pad used with this machine can include a body having a planarizing medium, an elongated first side edge, and an elongated second side edge opposite the first side edge. The body has a length sufficient to extend across the planarizing zone and wrap around the roller.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: September 16, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Dinesh Chopra
  • Patent number: 6616828
    Abstract: A recovery system for platinum electrolytic baths operating at low current densities is disclosed. An oxidizing system is provided in a closed-loop recirculation system for platinum plating at low current densities. The oxidizing system reoxidizes Pt+2 ions, which are typically formed at low current densities, to Pt+4 ions by using oxidizers, for example peroxide. A sensor may be also provided to detect the relative concentration of [Pt+2] ions to [Pt+4] ions and to tailor the relative concentrations to a predetermined level.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: September 9, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Dinesh Chopra
  • Publication number: 20030164291
    Abstract: A recovery system for platinum electrolytic baths operating at low current densities is disclosed. An oxidizing system is provided in a closed-loop recirculation system for platinum plating at low current densities. The oxidizing system reoxidizes Pt+2 ions, which are typically formed at low current densities, to Pt+4 ions by using oxidizers, for example peroxide. A sensor may be also provided to detect the relative concentration of [Pt+2] ions to [Pt+4] ions and to tailor the relative concentrations to a predetermined level.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 4, 2003
    Inventor: Dinesh Chopra
  • Patent number: 6613671
    Abstract: A conductive connection forming method includes forming a first layer including a first metal on a substrate and forming a second layer including a second metal different from the first metal on the first layer. At least a part of the first layer may be transformed to an alloy material including the first and second metals. A conductive connection may be formed to the alloy material. The alloy material may be less susceptible to formation of metal oxide compared to the first metal. By way of example, transforming the first layer may include annealing the first and second layer. An exemplary first metal includes copper, and an exemplary second metal includes aluminum, titanium, palladium, magnesium, or two or more such metals. The alloy material may be an intermetallic. A conductive connection may be formed to the alloy layer. An integrated circuit includes a semiconductive substrate, a layer including a first metal over the substrate, and a layer of alloy material within the first metal including layer.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Fred Fishburn
  • Patent number: 6609957
    Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: August 26, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Dinesh Chopra, Scott G. Meikle