Abstract: A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a fixed-abrasive type polishing pad with a substantially abrasive-free slurry in which copper is removed at a rate that is substantially the same as or faster than a rate at which a material, such as tungsten, of the barrier layer is removed. The slurry is formulated so as to oxidize copper at substantially the same rate as or at a faster rate than a material of the barrier layer is oxidized. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry or the oxidation energy of the barrier layer material in the slurry may be greater than that of copper. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate is engaged with a planarizing medium that includes a planarizing pad and a planarizing liquid, at least one of which includes a chemical agent that removes a corrosion-inhibiting agent from discrete elements (such as abrasive particles) of the planarizing medium and/or impedes the corrosion-inhibiting agent from coupling to the discrete elements. The chemical agent can act directly on the corrosion-inhibiting agent or can first react with a constituent of the planarizing liquid to form an altered chemical agent, which then interacts with the corrosion-inhibiting agent. Alternatively, the altered chemical agent can control other aspects of the manner by which material is removed from the microelectronic substrate, for example, the material removal rate.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Abstract: method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate is engaged with a planarizing medium that includes a planarizing pad and a planarizing liquid. The planarizing liquid has a selected pH and abrasive elements in the planarizing pad have an isoelectric point that is at or below the pH of the planarizing liquid. For example, the abrasive elements can include coated or conglomerate elements formed from two materials, each having a different isoelectric point. Alternatively, different abrasive elements in the planarizing pad can have different isoelectric points. Accordingly, the abrasive elements can have a reduced affinity for components of the planaring liquid, such as corrosion-inhibiting agents. In another embodiment, high-frequency radiation, such as ultraviolet radiation, is directed toward the planarizing medium to control an amount of the corrosion-inhibiting agent adsorbed to the abrasive elements.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: Apparatuses and methods for planarizing a microelectronic-device substrate assembly on a planarizing pad. In one aspect of the invention, material is removed from the substrate assembly by pressing the substrate assembly against a planarizing surface of a planarizing pad and moving the substrate assembly across the planarizing surface through a planarizing zone. The method also includes replacing at least a portion of a used volume of planarizing solution on the planarizing surface with fresh planarizing solution during the planarization cycle of a single substrate assembly. The used planarizing solution can be replaced with fresh planarizing solution by actively removing the used planarizing solution from the pad with a removing unit and depositing fresh planarizing solution onto the pad in the planarizing zone.

Abstract: A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

Abstract: A system of cleaning a CMP pad used for removing copper from a substrate, the system comprising an abrasive cleaning pad, a cleaning solution delivery system that delivers a cleaning solution, an analyzing system that monitors the characteristics of the cleaning solution optically and chemically, and a carriage that allows the analyzing system to monitor the cleaning solution at a plurality of locations on the CMP pad. The use of the abrasive cleaning pad and the cleaning solution removes contaminants from the CMP pad, and the contaminants are dissolved in the cleaning solution. By measuring the concentration of contaminants in the cleaning solution, the condition of the CMP pad can be monitored. To measure the concentration of the contaminants, changes in the refractive index and absorption of light in the cleaning solution are measured, wherein the refractive index and absorption depend on the concentration of the contaminants.

Abstract: A barrier layer material and method of forming the same is disclosed. The method includes depositing a graded metal nitride layer in a single deposition chamber, with a high nitrogen content at a lower surface and a high metal content at an upper surface. In the illustrated embodiment, a metal nitride with a 1:1 nitrogen-to-metal ratio is initially deposited into a deep void, such as a via or trench, by reactive sputtering of a metal target in nitrogen atmosphere. After an initial thickness is deposited, flow of nitrogen source gas is reduced and sputtering continues, producing a metal nitride with a graded nitrogen content. After the nitrogen is stopped, deposition continues, resulting in a substantially pure metal top layer. This three-stage layer includes a highly conductive top layer, upon which copper can be directly electroplated without a separate seed layer deposition.

Abstract: A method of forming a metal seed layer, preferably a copper layer, for subsequent electrochemical deposition. The metal seed layer is formed by the oxidation-reduction reaction of a metal salt with a reducing agent present in a layer on the substrate to be plated. Metal interconnects for semiconductor devices may be produced by the method, which has the advantage of forming the metal seed layer by a simple electrochemical plating process that may be combined with the plating of the interconnect itself as a single-bath operation.

Abstract: A recovery system for platinum electrolytic baths operating at low current densities is disclosed. An oxidizing system is provided in a closed-loop recirculation system for platinum plating at low current densities. The oxidizing system reoxidizes Pt+2 ions, which are typically formed at low current densities, to Pt+4 ions by using oxidizers, for example peroxide. A sensor may be also provided to detect the relative concentration of [Pt+2] ions to [Pt+4] ions and to tailor the relative concentrations to a predetermined level.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: A method and apparatus for cleaning a web-based chemical-mechanical planarization (CMP) system. Specifically, a fluid spray bar is coupled to a frame assembly which may be mounted on a CMP system. The fluid spray bar will move along the frame assembly. As the fluid spray bar traverses the length of the frame assembly, a cleaning fluid is sprayed onto the web in order to clean the web between planarization cycles.