Abstract: Proposed are a process fluid treatment apparatus capable of decomposing ozone in a process fluid more effectively, and a wafer cleaning apparatus and semiconductor manufacturing equipment including the same. The process fluid treatment apparatus treats the process fluid used for cleaning a wafer in the semiconductor manufacturing equipment, and includes a housing having an inner space configured to contain the process fluid, a spray nozzle configured to spray the process fluid containing ozone into the inner space in the form of mist, and a nozzle heater configured to heat the process fluid passing through the spray nozzle.

Abstract: Provided is a compound of Chemical Formula 1 or 2: wherein: R1 to R4 are each independently hydrogen or deuterium; n1 to n4 are an integer of 1 to 4; L1 and L2 are each independently a direct bond or a substituted or unsubstituted C6-60 arylene; and Ar1 and Ar2 are each independently a substituent of Chemical Formula 3: wherein X1 to X5 are each independently N or C(R5), wherein at least two of X1 to X5 are N; and each R5 is independently hydrogen, deuterium, a substituted or unsubstituted C1-20 alkyl, a substituted or unsubstituted C6-60 aryl, or a substituted or unsubstituted C2-60 heteroaryl containing at least one of N, O and S, or two adjacent R5s combine to form a benzene ring; and an organic light emitting device including the same. The device exhibits significantly superior efficiency and lifespan.

Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.

Abstract: An integrated braking device for a vehicle equipped with wheel brakes includes a reservoir, master cylinder, bi-directional pumps each using hydraulic pressure oil from the reservoir for generating hydraulic pressure in first direction to apply braking force to the wheel brakes or generating hydraulic pressure in opposing second direction to control the hydraulic pressure oil from flowing to the reservoir, a hydraulic motor for driving the bi-directional pumps, inlet valves for controlling a hydraulic pressure from flowing from the bi-directional pumps to the wheel brakes, traction control valves each disposed between the master cylinder and each bi-directional pump to control flow of the hydraulic pressure oil inside the master cylinder, and a braking control unit for braking the vehicle by transmitting a driving signal to solenoid valves in the integrated braking device, the bi-directional pumps, and the hydraulic motor to control a flow of the hydraulic pressure.

Abstract: A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.

Abstract: Provided are a method and device for obtaining a position of a stationary target. The method of obtaining a position of a stationary target may include generating a fusion track based on data collected from a radar and data collected from a camera, determining whether the fusion track is in a stationary state, in response to the fusion track being in the stationary state, collecting radar points associated with the fusion track, and obtaining a center point of the stationary target based on the collected radar points.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Abstract: Disclosed herein are a decoding method and apparatus and an encoding method and apparatus that perform inter-prediction using a motion vector predictor. For a candidate block in a col picture, a scaled motion vector is generated based on a motion vector of the candidate block. When the scaled motion vector indicates a target block, a motion vector predictor of the target block is generated based on the motion vector of the candidate block. The motion vector predictor is used to derive the motion vector of the target block in a specific inter-prediction mode such as a merge mode and an AMVP mode.

Abstract: A stacked integrated circuit includes an upper chip that is rotated around a rotation axis and stacked on a lower chip in the form of a mirror symmetric structure. The lower chip and the upper chip are stacked in the form of a front and front connection structure. The upper chip is configured to generate a first internal distinguishment signal based on a distinguishment signal. The upper chip is configured to generate a first input/output control signal for the input/output of a power signal based on the first internal distinguishment signal and a chip selection signal. The lower chip is configured to generate a second internal distinguishment signal based on a reset signal. The lower chip is configured to generate a second input/output control signal for the input/output of the power signal based on the second internal distinguishment signal and the chip selection signal.

Abstract: A display device includes a via insulating layer on a substrate; a first electrode on the via insulating layer; a pixel defining layer including an inclined region on the first electrode and including a first opening exposing a portion of the first electrode, and a flat region at a side of the inclined region and in contact with the via insulating layer; a light emitting layer on the portion of the first electrode exposed by the first opening; organic particles on the flat region of the pixel defining layer; an encapsulation layer covering the pixel defining layer, the light emitting layer, and the organic particles, and including a first layer, a second layer, and a third layer; and a first light blocking layer on the third layer of the encapsulation layer to overlap the flat region of the pixel defining layer and form a second opening.

Abstract: An inkjet printing apparatus, method of printing ink using the same and method of fabricating display device are provided. The method of printing ink includes: ejecting ink in which a plurality of particles is dispersed from an inkjet head; irradiating the ejected ink with a first light and a second light having different wavelengths to acquire data on a first exit light and a second exit light emitted from the ink; calculating a concentration of the particles in the ink from the data on the first exit light and the second exit light; and checking whether the concentration is out of an error range from a reference value, where the first light has a wavelength of about 500 nm or less, and the second light has a wavelength of about 1000 nm or more.

Abstract: A display panel can include a substrate, a light-emitting element including an emission region on the substrate, a reference voltage line adjacent to the light-emitting element, and a branch line connected to the reference voltage line to apply a reference voltage to light-emitting element. The light-emitting element can emit light on the emission region in a direction of the substrate. Further, the branch line can include a semiconductor layer, and the semiconductor layer of the branch line can overlap the emission region.

Abstract: A display device includes: a first base having a display area; light-emitting elements on the first base; and an encapsulation layer over the light-emitting elements. The encapsulation layer includes: a first inorganic layer; an organic layer on the first inorganic layer; and a second inorganic layer on the organic layer. The first inorganic layer includes: a first buffer layer on the light-emitting elements; a first barrier layer on the first buffer layer; a first porous layer on the first barrier layer; a second barrier layer on the first porous layer; and a second buffer layer on the second barrier layer. A refractive index of the first buffer layer, the first barrier layer, and the first porous layer are different from one another, and the refractive index of the first porous layer is smaller than the refractive index of the first buffer layer and the first barrier layer.

Abstract: An apparatus for providing brain lesion information based on an image includes a magnetic resonance angiography (MRA) provider configured to provide an environment capable of displaying 3D time-of-flight magnetic resonance angiography (3D TOF MRA) using user input, a brain lesion input unit configured to generate and manage a brain lesion image, a maximum intensity projection (MIP) converter configured to configure MIP image data including at least one image frame corresponding to a projection position of the brain lesion image, a noise remover configured to remove noise of brain lesion information and to configure corrected MIP image data, from which the noise is removed, and an MRA reconfiguration unit configured to reconfigure a corrected brain lesion image by back-projecting the corrected MIP image data.

Abstract: A semiconductor device may include a source line, a bit line, and a gate structure located between the source line and the bit line. The gate structure may include conductive layers and insulating layers that are alternately stacked. The semiconductor device may include a topological insulator that may extend from the bit line to the source line through the gate structure. The topological insulator may include a non-conductor region and semiconductor regions coupled to the non-conductor region and located at a sidewall of the topological insulator. The semiconductor device may also include a memory layer surrounding the topological insulator.

Abstract: A CMOS device, and a method of manufacturing the same, includes a semiconductor substrate and a trench formed in the semiconductor substrate. The CMOS device also includes an oxide semiconductor layer disposed in the trench, the oxide semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region. The CMOS device further includes a buffer layer between the oxide semiconductor layer and the semiconductor substrate, a gate insulating layer on the oxide semiconductor layer, a gate electrode disposed on the gate insulating layer over the channel region of the oxide semiconductor layer, and impurities distributed in each of the source region and the drain region of the oxide semiconductor layer.

Abstract: The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller, based on detection information that indicates a state of the memory device, selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation was performed before the detecting, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase in threshold voltage of a threshold voltage distribution of the monitoring memory cells.

Abstract: The present disclosure provides a composition through which a laminate which is aesthetically excellent is formed by exhibiting a blue-based color, which is a general window color, and through which a laminate having high visible light transmittance and an excellent thermochromic property is formed while enabling mass production, and the present disclosure further provides a laminate formed through the above composition and a window including the laminate.

Abstract: A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Abstract: The present disclosure provides a chip including an even area including an even through via through which an even address is received and an even redundancy through via through which an even redundancy address is received, and an odd area including an odd through via through which an odd address is received and an odd redundancy through via through which an odd redundancy address is received. In the present disclosure, the even area may include an even address selection circuit configured to, based on a chip information signal, generate a selection even address and a selection even redundancy address from the even address, the even redundancy address, the odd address, and the odd redundancy address, and an even internal address generation circuit configured to, based on an even repair signal, generate an internal even address from the selection even address and the selection even redundancy address.