Abstract: Provided are a light-emitting element, a manufacturing method thereof, and a display device comprising the light-emitting element. The method for manufacturing the light-emitting element comprises the steps of: preparing a lower substrate including a substrate and a buffer material layer formed on the substrate, forming a separating layer disposed on the lower substrate and including at least one graphene layer, forming an element deposition structure by depositing a first conductivity type semiconductor layer, an active material layer, and a second conductivity type semiconductor layer on the separating layer, forming an element rod by etching the element deposition structure and the separating layer in a vertical direction; and separating the element rod from the lower substrate to form a light emitting element.

Abstract: A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.

Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a first stacked structure including a plurality of first electrode patterns and a plurality of first interlayer insulating layers that are alternately stacked on each other, a first vertical structure extending into the first stacked structure in a vertical direction, an insulating layer formed over the first stacked structure, a coupling structure passing through the insulating layer and formed over the first vertical structure, a second stacked structure including a plurality of second electrode patterns and a plurality of second interlayer insulating layers that are alternately stacked on each other over the insulating layer, and a second vertical structure extending into the second stacked structure in the vertical direction and formed over the coupling structure.

Abstract: Provided are a system and a method for managing an unmanned store remotely, particularly a system and a method that can remotely perform unmanned store management, including door control, lighting control, kiosk management, etc., using Internet of Things (IoT) technology.

Abstract: A switching element comprising: a first gate dielectric layer formed over a substrate; a second gate dielectric layer formed over the first gate dielectric layer to overlap a part of the first gate dielectric layer, and including a ferroelectric material; a second gate electrode formed over the second gate dielectric layer; and a first gate electrode located between the first and second gate dielectric layers, and configured to control the second gate dielectric layer to selectively have negative capacitance.

Abstract: Proposed are a process fluid treatment apparatus capable of decomposing ozone in a process fluid more effectively, and a wafer cleaning apparatus and semiconductor manufacturing equipment including the same. The process fluid treatment apparatus treats the process fluid used for cleaning a wafer in the semiconductor manufacturing equipment, and includes a housing having an inner space configured to contain the process fluid, a spray nozzle configured to spray the process fluid containing ozone into the inner space in the form of mist, and a nozzle heater configured to heat the process fluid passing through the spray nozzle.

Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.

Abstract: An integrated braking device for a vehicle equipped with wheel brakes includes a reservoir, master cylinder, bi-directional pumps each using hydraulic pressure oil from the reservoir for generating hydraulic pressure in first direction to apply braking force to the wheel brakes or generating hydraulic pressure in opposing second direction to control the hydraulic pressure oil from flowing to the reservoir, a hydraulic motor for driving the bi-directional pumps, inlet valves for controlling a hydraulic pressure from flowing from the bi-directional pumps to the wheel brakes, traction control valves each disposed between the master cylinder and each bi-directional pump to control flow of the hydraulic pressure oil inside the master cylinder, and a braking control unit for braking the vehicle by transmitting a driving signal to solenoid valves in the integrated braking device, the bi-directional pumps, and the hydraulic motor to control a flow of the hydraulic pressure.

Abstract: A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.

Abstract: A stacked integrated circuit includes an upper chip that is rotated around a rotation axis and stacked on a lower chip in the form of a mirror symmetric structure. The lower chip and the upper chip are stacked in the form of a front and front connection structure. The upper chip is configured to generate a first internal distinguishment signal based on a distinguishment signal. The upper chip is configured to generate a first input/output control signal for the input/output of a power signal based on the first internal distinguishment signal and a chip selection signal. The lower chip is configured to generate a second internal distinguishment signal based on a reset signal. The lower chip is configured to generate a second input/output control signal for the input/output of the power signal based on the second internal distinguishment signal and the chip selection signal.

Abstract: A semiconductor device may include a source line, a bit line, and a gate structure located between the source line and the bit line. The gate structure may include conductive layers and insulating layers that are alternately stacked. The semiconductor device may include a topological insulator that may extend from the bit line to the source line through the gate structure. The topological insulator may include a non-conductor region and semiconductor regions coupled to the non-conductor region and located at a sidewall of the topological insulator. The semiconductor device may also include a memory layer surrounding the topological insulator.

Abstract: A CMOS device, and a method of manufacturing the same, includes a semiconductor substrate and a trench formed in the semiconductor substrate. The CMOS device also includes an oxide semiconductor layer disposed in the trench, the oxide semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region. The CMOS device further includes a buffer layer between the oxide semiconductor layer and the semiconductor substrate, a gate insulating layer on the oxide semiconductor layer, a gate electrode disposed on the gate insulating layer over the channel region of the oxide semiconductor layer, and impurities distributed in each of the source region and the drain region of the oxide semiconductor layer.

Abstract: The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller, based on detection information that indicates a state of the memory device, selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation was performed before the detecting, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase in threshold voltage of a threshold voltage distribution of the monitoring memory cells.

Abstract: The present disclosure provides a composition through which a laminate which is aesthetically excellent is formed by exhibiting a blue-based color, which is a general window color, and through which a laminate having high visible light transmittance and an excellent thermochromic property is formed while enabling mass production, and the present disclosure further provides a laminate formed through the above composition and a window including the laminate.

Abstract: A stacked integrated circuit includes a first chip including a first area and a second area that are disposed to be substantially symmetrical to each other in relation to a first rotating axis. The first area includes a first through via set and a first front pad set that are connected by using a first connection method. The second area includes a second through via set and a second front pad set that are connected by using a second connection method. The first through via set and the second through via set are disposed to be substantially symmetrical to each other in relation to the first rotating axis. The first front pad set and the second front pad set are disposed to be substantially symmetrical to each other in relation to the first rotating axis.

Abstract: A stacked integrated circuit includes a first chip including a first through via set and a second through via set that are disposed to be symmetrical to each other in relation to a first rotating axis and including a first input and output (IO) circuit and a second IO circuit that are disposed to be asymmetrical to each other in relation to the first rotating axis and a second chip including a third through via set and a fourth through via set that are disposed to be symmetrical to each other in relation to a second rotating axis and including a third IO circuit and a fourth IO circuit that are disposed to be asymmetrical to each other in relation to the second rotating axis, the second chip being rotated around the second rotating axis and stacked on the first chip.

Abstract: The present disclosure provides a chip including an even area including an even through via through which an even address is received and an even redundancy through via through which an even redundancy address is received, and an odd area including an odd through via through which an odd address is received and an odd redundancy through via through which an odd redundancy address is received. In the present disclosure, the even area may include an even address selection circuit configured to, based on a chip information signal, generate a selection even address and a selection even redundancy address from the even address, the even redundancy address, the odd address, and the odd redundancy address, and an even internal address generation circuit configured to, based on an even repair signal, generate an internal even address from the selection even address and the selection even redundancy address.

Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.

Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.