Abstract: A memory system memory system includes a first chip configured to perform a first operation, a second chip configured to perform a second operation, and a stacked memory device including a stacked structure of a plurality of memories. The stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus.

Abstract: A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.

Abstract: Provided is a pharmaceutical composition for preventing or treating neuronal diseases comprising, as an active ingredient, an exon 2-deleted AIMP2 variant (AIMP2-DX2) gene or a vector comprising the gene, and a method for treating neuronal diseases in animals other than humans, comprising administering the same to a subject in need of treatment. The pharmaceutical composition comprising, as an active ingredient, a AIMP2-DX2 gene or a vector comprising the gene has the effects of apoptosis inhibition, dyskinesia amelioration and oxidative stress inhibition and thus can be widely used for preventing and treating neuronal diseases such as Parkinson's disease and amyotrophic lateral sclerosis.

Abstract: A controller comprises an error correction circuit configured to check an error bit number of error bits in the read data and correct the error bits; a read retry range setting circuit configured to reset a preset read retry range with respect to the read data, and set a new read retry range based on the error bit number and an error correction capability of the error correction circuit; a read voltage setting circuit configured to reset the set read voltage and set, as a new read voltage, a voltage among a plurality of voltages of the reset read retry range, corresponding to the new read retry range; and a flash control circuit configured to control the memory device to perform a read retry operation on the stored data, using the new read voltage.

Abstract: The present disclosure relates to a resin composition for vehicle parts, a vehicle part manufactured using the resin composition, and a method of manufacturing the vehicle part. Ultra-high molecular weight siloxane and an inorganic filler are mixed with an alloy resin of polyamide and polyethylene at an optimal rate in order to improve friction resistance and wear resistance while maintaining excellent impact resistance and low hygroscopicity. When a vehicle part is manufactured using the resin composition, it is possible to eliminate the application of silicone-based oil or to remarkably reduce the amount of silicone-based oil that is used, whereby it is possible to reduce manufacturing costs. Furthermore, ingredients that are harmful to human beings, such as POM, are not included, whereby it is possible to improve the quality of air in a vehicle.

Abstract: The present disclosure relates to an electronic device. A storage device having improved reliability may include a memory device performing a program operation of storing data in selected memory cells, among a plurality of memory cells included in a memory block, and a memory controller controlling the memory device to perform a retention control operation of applying a retention control voltage to at least one source line coupled to a plurality of memory cell strings included in the memory block for a predetermined time duration when the program operation is completed.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: A memory system memory system includes a first chip configured to perform a first operation, a second chip configured to perform a second operation, and a stacked memory device including a stacked structure of a plurality of memories. The stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus.

Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.

Abstract: A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. The output enable signal may initiate a data transfer operation.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.

Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.

Abstract: Provided herein, inter alia, are a carbon fiber-reinforced polymer composite and a method for manufacturing the same. The carbon fiber-reinforced polymer composite may improve interfacial bonding force by modifying the surface of carbon fibers with an amphiphilic block copolymer and then forming a composite of the surface-modified carbon fibers with a polymer.

Abstract: Disclosed is an OLED device which is capable of preventing a source voltage of a driving transistor so as to compensate for a deterioration of an organic light emitting diode from being out of a sensing voltage range of an analog-to-digital converter, and a method for driving the same, wherein a sensing timing is controlled in such a way that the source voltage of the driving transistor sensed for a sensing mode is included within the sensing voltage range. Accordingly, it is possible to prevent the source voltage of the driving transistor from being out of the sensing voltage range of the analog-to-digital converter.

Abstract: The present disclosure relates to an electronic device. A storage device having improved reliability may include a memory device performing a program operation of storing data in selected memory cells, among a plurality of memory cells included in a memory block, and a memory controller controlling the memory device to perform a retention control operation of applying a retention control voltage to at least one source line coupled to a plurality of memory cell strings included in the memory block for a predetermined time duration when the program operation is completed.

Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.

Abstract: Provided is a tire capable of efficiently discharging water, which is additionally absorbed through a plurality of flow tubes, through the flow tubes and a drain tube, thereby improving wet grip performance. The tire with enhanced wet grip includes a kerf formed on a block to discharge water introduced thereinto to a groove, a drain tube formed in the kerf in its longitudinal direction and connected to the groove to discharge the water to the groove, and a flow tube formed in the kerf toward the drain tube from an inlet of the kerf, into which the water is introduced, and connected to the groove or the drain tube.

Abstract: Provided is a pharmaceutical composition for preventing or treating neuronal diseases comprising, as an active ingredient, an exon 2-deleted AIMP2 variant (AIMP2-DX2) gene or a vector comprising the gene, and a method for treating neuronal diseases in animals other than humans, comprising administering the same to a subject in need of treatment. The pharmaceutical composition comprising, as an active ingredient, a AIMP2-DX2 gene or a vector comprising the gene has the effects of apoptosis inhibition, dyskinesia amelioration and oxidative stress inhibition and thus can be widely used for preventing and treating neuronal diseases such as Parkinson's disease and amyotrophic lateral sclerosis.

Abstract: A semiconductor device includes a first integrated chip; a second integrated chip; a plurality of reference through-chip vias formed through the first and second integrated circuit chips; and at least a normal through-chip via formed through the first and second integrated circuit chips, wherein the first integrated circuit chip comprises: a plurality of reference sourcing circuits suitable for sourcing a reference current to the respective reference through-chip vias; and at least a sourcing circuit suitable for sourcing the reference current to the normal through-chip via, and wherein the second integrated circuit chip comprises: a plurality of reference sinking circuits suitable for sinking currents flowing through the respective reference through-chip vias; a line suitable for electrically coupling the plurality of reference through-chip vias; a comparison voltage generation circuit suitable for generating a plurality of comparison voltages based on a voltage of the line; at least a sinking circuit suitab