Patents by Inventor Dong-Uk Lee

Dong-Uk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176040
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Dong Kyun KIM, Min Su PARK
  • Publication number: 20200174952
    Abstract: A memory system memory system includes a first chip configured to perform a first operation, a second chip configured to perform a second operation, and a stacked memory device including a stacked structure of a plurality of memories. The stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus.
    Type: Application
    Filed: March 13, 2019
    Publication date: June 4, 2020
    Inventor: Dong Uk LEE
  • Publication number: 20200160919
    Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Inventors: Dong Uk LEE, Jae Hyuk BANG
  • Patent number: 10613577
    Abstract: A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. The output enable signal may initiate a data transfer operation.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Hak Song Kim, Dong Kyun Kim, Dong Uk Lee
  • Patent number: 10586577
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 10, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Dong Kyun Kim, Min Su Park
  • Patent number: 10580500
    Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Jae Hyuk Bang
  • Patent number: 10566266
    Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Heat Bit Park, Ji Hwan Kim, Dong Uk Lee
  • Patent number: 10557019
    Abstract: Provided herein, inter alia, are a carbon fiber-reinforced polymer composite and a method for manufacturing the same. The carbon fiber-reinforced polymer composite may improve interfacial bonding force by modifying the surface of carbon fibers with an amphiphilic block copolymer and then forming a composite of the surface-modified carbon fibers with a polymer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 11, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Korea University Research and Business Foundation
    Inventors: Sung Hyun Lee, Soon Joon Jung, Won Jin Seo, Dong Uk Lee, Ho Gyu Yoon, Heun Young Seo, Yong Sik Yeom, Jae Young Lee
  • Patent number: 10522082
    Abstract: Disclosed is an OLED device which is capable of preventing a source voltage of a driving transistor so as to compensate for a deterioration of an organic light emitting diode from being out of a sensing voltage range of an analog-to-digital converter, and a method for driving the same, wherein a sensing timing is controlled in such a way that the source voltage of the driving transistor sensed for a sensing mode is included within the sensing voltage range. Accordingly, it is possible to prevent the source voltage of the driving transistor from being out of the sensing voltage range of the analog-to-digital converter.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: December 31, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: YongKon Lee, Dong-Uk Lee
  • Publication number: 20190392901
    Abstract: The present disclosure relates to an electronic device. A storage device having improved reliability may include a memory device performing a program operation of storing data in selected memory cells, among a plurality of memory cells included in a memory block, and a memory controller controlling the memory device to perform a retention control operation of applying a retention control voltage to at least one source line coupled to a plurality of memory cell strings included in the memory block for a predetermined time duration when the program operation is completed.
    Type: Application
    Filed: December 28, 2018
    Publication date: December 26, 2019
    Inventors: Dong Uk LEE, Se Chang PARK
  • Publication number: 20190371371
    Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.
    Type: Application
    Filed: December 17, 2018
    Publication date: December 5, 2019
    Inventors: Heat-Bit PARK, Ji-Hwan KIM, Dong-Uk LEE
  • Publication number: 20190329598
    Abstract: Provided is a tire capable of efficiently discharging water, which is additionally absorbed through a plurality of flow tubes, through the flow tubes and a drain tube, thereby improving wet grip performance. The tire with enhanced wet grip includes a kerf formed on a block to discharge water introduced thereinto to a groove, a drain tube formed in the kerf in its longitudinal direction and connected to the groove to discharge the water to the groove, and a flow tube formed in the kerf toward the drain tube from an inlet of the kerf, into which the water is introduced, and connected to the groove or the drain tube.
    Type: Application
    Filed: December 3, 2018
    Publication date: October 31, 2019
    Inventors: Jae Gang PARK, Dong Uk LEE, Ha Eun KOOG
  • Publication number: 20190298858
    Abstract: Provided is a pharmaceutical composition for preventing or treating neuronal diseases comprising, as an active ingredient, an exon 2-deleted AIMP2 variant (AIMP2-DX2) gene or a vector comprising the gene, and a method for treating neuronal diseases in animals other than humans, comprising administering the same to a subject in need of treatment. The pharmaceutical composition comprising, as an active ingredient, a AIMP2-DX2 gene or a vector comprising the gene has the effects of apoptosis inhibition, dyskinesia amelioration and oxidative stress inhibition and thus can be widely used for preventing and treating neuronal diseases such as Parkinson's disease and amyotrophic lateral sclerosis.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Jin Woo Choi, Dong Uk Lee, Ki Hwan Eum
  • Publication number: 20190293711
    Abstract: A semiconductor device includes a first integrated chip; a second integrated chip; a plurality of reference through-chip vias formed through the first and second integrated circuit chips; and at least a normal through-chip via formed through the first and second integrated circuit chips, wherein the first integrated circuit chip comprises: a plurality of reference sourcing circuits suitable for sourcing a reference current to the respective reference through-chip vias; and at least a sourcing circuit suitable for sourcing the reference current to the normal through-chip via, and wherein the second integrated circuit chip comprises: a plurality of reference sinking circuits suitable for sinking currents flowing through the respective reference through-chip vias; a line suitable for electrically coupling the plurality of reference through-chip vias; a comparison voltage generation circuit suitable for generating a plurality of comparison voltages based on a voltage of the line; at least a sinking circuit suitab
    Type: Application
    Filed: November 26, 2018
    Publication date: September 26, 2019
    Inventor: Dong-Uk LEE
  • Patent number: 10424355
    Abstract: A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: September 24, 2019
    Assignee: SK hynix Inc.
    Inventors: Dong-Uk Lee, Young-Ju Kim, Keun-Soo Song
  • Publication number: 20190267076
    Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.
    Type: Application
    Filed: September 5, 2018
    Publication date: August 29, 2019
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Ji Hwan KIM, Heat Bit PARK
  • Patent number: 10372157
    Abstract: A semiconductor device includes a phase comparison circuit, an output enablement signal generation circuit, and a data input/output (I/O) circuit. The phase comparison circuit compares a phase of a clock signal with a phase of a delay locked loop (DLL) clock signal to generate a phase information signal. The output enablement signal generation circuit latches an internal command in response to a first pre-control signal and outputs the latched internal command as an output enablement signal in response to an operation clock signal and a second pre-control signal. The output enablement signal generation circuit generates the first pre-control signal according to an internal clock signal and an input clock signal. The data I/O circuit receives input data and output the received input data as output data synchronized with a strobe signal in response to the output enablement signal.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 6, 2019
    Assignee: SK HYNIX INC.
    Inventor: Dong Uk Lee
  • Publication number: 20190171359
    Abstract: A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 6, 2019
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Kyung Whan KIM
  • Patent number: 10291209
    Abstract: A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first MOS transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second MOS transistor.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 14, 2019
    Assignee: SK hynix Inc.
    Inventors: Kyung Whan Kim, Dong Uk Lee
  • Publication number: 20190115083
    Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.
    Type: Application
    Filed: May 23, 2018
    Publication date: April 18, 2019
    Inventors: Dong Uk LEE, Jae Hyuk BANG