Abstract: A memory subsystem with memory managed with coherent access can manage page table entries to enable putting the memory in a low power state. The memory control can change a page table entry for the memory prior to triggering the memory to enter the low power state. The change to the page table entry will cause a page fault for a subsequent access to the memory. The page fault will trigger handling the access to the memory with a fault routine, avoiding synchronous delay to the memory that would occur with normal access.

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

Abstract: A device includes a printed circuit board (PCB) and a shield for the PCB. The shield can reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads to interface with a corresponding connector. For example, for a dual inline memory module (DIMM) PCB, the PCB includes pads to insert into a DIMM connector. The shield includes a gap in its perimeter that aligns with clips in the corresponding connector. The gaps will correspond to similar features of the PCB that interface with the corresponding connector to allow the shield to attach to the PCB. The shield includes lock fingers to extend from a connector-facing edge of the shield to interface with the corresponding connector to align the shield with the corresponding connector.

Abstract: Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Abstract: A glass sheet processing system for processing a glass sheet includes a conveyor for conveying the glass sheet in a direction of conveyance, and a positioning apparatus for adjusting position of the glass sheet on the conveyor. The positioning apparatus includes a movable carriage having first and second carriage bodies. The first carriage body is translatable in the direction of conveyance, and the second carriage body is supported by the first carriage body such that the second carriage body is movable in a direction generally transverse to the direction of conveyance. The positioning apparatus further includes a first drive assembly for moving the first carriage body in the direction of conveyance, a second drive assembly for moving the second carriage body with respect to the first carriage body, and a positioner member connected to the second carriage body for contacting the glass sheet to adjust position of the glass sheet.

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

Abstract: Articles of footwear may include a knitted component defining at least part of a void and joined with a sole structure. The knitted component may include an interior knit layer, an exterior knit layer, and a plurality of inlaid courses of a high tenacity yarn between the interior and exterior knit layers. The plurality of inlaid courses of high tenacity yarn may include at least three courses of the high tenacity yarn, each of which may be separated from an adjacent course of the plurality by no more than five courses.

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Abstract: An invertible optical float switch is provided, comprising a floatable housing having an interior, a central longitudinal axis, a top end and a bottom end; first and second optical fibers each having proximal and distal ends, the proximal end of the first optical fiber connectable to a light source located remote from the housing, the proximal end of the second optical fiber connectable to a light detector located remote from the housing, the distal ends of the first and optical fibers positioned in the interior of the housing and the distal ends being mounted in the interior on a separator assembly such that the distal ends are optically aligned and separated by a gap; the separator assembly further including a movable member, the movable member adapted to be movable by gravity between a first position where the movable member occupies the gap such that the distal ends are no longer optically aligned, and a second position where the movable member does not occupy the gap; wherein the distal ends and the sepa

Abstract: Knitted components may include a first knit layer including a first yarn, a second knit layer, and a plurality of inlaid courses of a high tenacity yarn having a tenacity of at least six grams-force per denier. The plurality of inlaid courses of the high tenacity yarn may include at least three courses of high tenacity yarn, each of which may be separated from an adjacent course of the first plurality of courses of the high tenacity yarn by no more than five courses of the first yarn.

Abstract: Articles of footwear may include a knitted component defining at least part of a void and joined with a sole structure. The knitted component may include an interior knit layer, an exterior knit layer, and a plurality of inlaid courses of a high tenacity yarn between the interior and exterior knit layers. The plurality of inlaid courses of high tenacity yarn may include at least three courses of the high tenacity yarn, each of which may be separated from an adjacent course of the plurality by no more than five courses.

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

Abstract: An interconnectable locking module having a first portion including an external surface defining a bulbous connector extending along a longitudinal axis; a second portion opposite of the first portion, the second portion includes an interior surface defining a hollow receptacle, and an opposite exterior surface defining a circumferential flange having a tapered channel. The tapered channel includes a channel opening and an opposite closed end. The module also includes a locking ring having an interior circumferential surface insertable over the bulbous connector and engageable with the circumferential flange. The locking ring includes a tab insertable into the channel opening and slidable against a tapered channel surface. A plurality of interconnectable locking module may be joined in series to provide an assembly such as a physical model representing a prototype conduit or a path for a conduit.