Abstract: A glass sheet processing system for processing a glass sheet includes a conveyor for conveying the glass sheet in a direction of conveyance, and a positioning apparatus for adjusting position of the glass sheet on the conveyor. The positioning apparatus includes a movable carriage having first and second carriage bodies. The first carriage body is translatable in the direction of conveyance, and the second carriage body is supported by the first carriage body such that the second carriage body is movable in a direction generally transverse to the direction of conveyance. The positioning apparatus further includes a first drive assembly for moving the first carriage body in the direction of conveyance, a second drive assembly for moving the second carriage body with respect to the first carriage body, and a positioner member connected to the second carriage body for contacting the glass sheet to adjust position of the glass sheet.

Abstract: Knitted components may include a first knit layer including a first yarn, a second knit layer, and a plurality of inlaid courses of a high tenacity yarn having a tenacity of at least six grams-force per denier. The plurality of inlaid courses of the high tenacity yarn may include at least three courses of high tenacity yarn, each of which may be separated from an adjacent course of the first plurality of courses of the high tenacity yarn by no more than five courses of the first yarn.

Abstract: A memory device includes a grounded molding. The memory device includes a substrate having a first surface for a memory die, where the substrate has ground vias through substrate to connect to a ground reference. The substrate has a ball grid array (BGA) on the opposite surface, including perimeter balls to connect to ground connections. The grounded molding includes an electrically conductive epoxy mold to cover the memory die, where the electrical conductivity of the molding, with the molding grounded can provide radio frequency interference (RFI) shielding.

Abstract: A windscreen wiper device for cleaning a windshield of a vehicle is provided. The windscreen wiper device includes a wiper strip for sealing against the windshield and at least one carrier element engaged with the wiper strip to bias the wiper strip into a predetermined configuration. A frame structure is coupled to the at least one carrier element and includes at least two components. One of the components presents an elongated member with a resilient tab, and another component includes a longitudinally extending opening. One of the walls of the opening has a recess shaped similarly to the resilient tab. The elongated member is inserted into the opening until the resilient tab snaps into the opening to interconnect the components.

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

Abstract: A method comprising: providing a powder composition including at least one ultrafine, spherical thermoplastic polymer powder having a glass transition temperature (Tg) of at least 150 degrees C.; and powder bed fusing the powder composition to form a three-dimensional article.

Abstract: One embodiment provides a method, including: detecting, in an overlay input application, one or more ink strokes provided to an input field overlay area; and providing, in the overlay input application, a preview area that displays a typeset preview for the one or more ink strokes; wherein the preview area is displayed in a location determined by an area associated with current ink stroke input. Other embodiments are described and claimed.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: Disclosed herein are methods that includes using a water-degradable (e.g., autoclavable) support material together with a high-heat build material (e.g., polyetherimide or PEI). When the support material is autoclaved for a period of time, the support material becomes brittle and then disintegrates into powder and therefore can be removed from the model or build material, leaving behind a part formed from the model material that includes features (e.g., cavities, channels, etc.) formerly occupied by the support material.

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

Abstract: One embodiment provides a method, including: accepting, in an input and display device, handwriting ink strokes; providing, using a handwriting recognition engine, one or more machine words for the one or more ink strokes; determining a characteristic of the one or more handwriting ink strokes; changing, based on the characteristic of the handwriting ink strokes, input formatting for the one or more machine words; and inputting the one or more machine words according to the input formatting. Other embodiments are described and claimed.

Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.

Abstract: Examples include techniques to change a mode of operation for a memory device. Examples include using information stored at a memory array of the memory device to program mode registers at the memory device to change the mode of operation to a first mode of operation that corresponds to a frequency set point associated with dynamic voltage and frequency scaling for a processor coupled with the memory device.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

Abstract: Remote monitoring of operating parameters of equipment associated with renal treatments (e.g., hemodialysis and/or peritoneal dialysis) may include using a processor and computer-readable medium operably connected to the equipment and capable of receiving and storing data related to the operating parameters of the equipment. The system may be configured to: translate the received data related to the operating parameters of the equipment; determine a risk of malfunction of the equipment based on a comparison of the translated data for a respective operating parameter of the equipment against a predetermined limit for the respective operating parameter; and generate a report indicating the operating parameters and the determined malfunction risks of the equipment. The equipment may be remotely accessible, e.g. over a network, for monitoring of the data related to the operating parameters.

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.