Abstract: A retrofit door locking system is for being attached to an existing door. The system has a bolt receiver affixed to the door frame and a mounting plate. The mounting plate has a bolt tube that carries a slidable bolt. The bolt slides inside the tube and can be affixed between a retracted and extended position with a lock or a cotter pin. The bolt can be affixed by a lock that extends into grooves on the bolt or through a cotter pin that extends through a transverse hole. Along with being used to lock the door closed, the door can be prevented from latching by extending the bolt and locking it in the extended position.

Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Abstract: Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

Abstract: A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

Abstract: Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.

Abstract: Knitted components may include a first knit layer including a first yarn, a second knit layer, and a plurality of inlaid courses of a high tenacity yarn having a tenacity of at least six grams-force per denier. The plurality of inlaid courses of the high tenacity yarn may include at least three courses of high tenacity yarn, each of which may be separated from an adjacent course of the first plurality of courses of the high tenacity yarn by no more than five courses of the first yarn.

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

Abstract: Articles of footwear may include a knitted component defining at least part of a void and joined with a sole structure. The knitted component may include an interior knit layer, an exterior knit layer, and a plurality of inlaid courses of a high tenacity yarn between the interior and exterior knit layers. The plurality of inlaid courses of high tenacity yarn may include at least three courses of the high tenacity yarn, each of which may be separated from an adjacent course of the plurality by no more than five courses.

Abstract: A device includes a printed circuit board (PCB) and a shield for the PCB. The shield can reduce high frequency electromagnetic frequency (EMF) noise generated by one or more components of the PCB. The PCB includes pads to interface with a corresponding connector. For example, for a dual inline memory module (DIMM) PCB, the PCB includes pads to insert into a DIMM connector. The shield includes a gap in its perimeter that aligns with clips in the corresponding connector. The gaps will correspond to similar features of the PCB that interface with the corresponding connector to allow the shield to attach to the PCB. The shield includes lock fingers to extend from a connector-facing edge of the shield to interface with the corresponding connector to align the shield with the corresponding connector.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: Disclosed herein are methods that includes using a water-degradable (e.g., autoclavable) support material together with a high-heat build material (e.g., polyetherimide or PEI). When the support material is autoclaved for a period of time, the support material becomes brittle and then disintegrates into powder and therefore can be removed from the model or build material, leaving behind a part formed from the model material that includes features (e.g., cavities, channels, etc.) formerly occupied by the support material.

Abstract: The wiper device includes a wiper blade which extends in a longitudinal direction and at least one longitudinal strip that is pre-curved to have a curved shape when in a relaxed condition. The wiper device supports the wiper blade and biases the wiper blade into a curved shape. A connecting device is attached with the at least one longitudinal strip. The connecting device includes a two-piece base and a joint part which is pivotably connected with the two-piece base. The two-piece base includes a first piece, which is directly secured with the at least one longitudinal strip, and a second piece with laterally spaced apart side walls that are each J-shaped.

Abstract: An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.

Abstract: A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

Abstract: Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.