Abstract: A method for accessing a memory space allocated to a virtual machine, the method includes: receiving a request from the virtual machine to generate, for another virtual machine, a memory credential associated with a certain memory space allocated to the virtual machine; generating, in response to the request, a cryptographically signed credential; sending the cryptographically signed credential to the other virtual machine; receiving from the other virtual machine an access request to access at least one memory entry within the certain memory space; and accessing the at least one memory entry, if the access request complies with the memory credential.

Abstract: A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

Abstract: A method for accessing a memory space allocated to a virtual machine, the method includes: receiving a request from the virtual machine to generate, for another virtual machine, a memory credential associated with a certain memory space allocated to the virtual machine; generating, in response to the request, a cryptographically signed credential; sending the cryptographically signed credential to the other virtual machine; receiving from the other virtual machine an access request to access at least one memory entry within the certain memory space; and accessing the at least one memory entry, if the access request complies with the memory credential.

Abstract: A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

Abstract: A method of validating a configuration of a computer clusters includes transmitting a first neighbor identification to a first flexible service processor (FSP) arranged in the first computer cluster and a second neighbor identification to a second FSP arranged in the second computer cluster, connecting a first end of a cable to a first transceiver arranged in the first cluster and connecting a second end of the cable to a second transceiver arranged in the second cluster. The first neighbor identification is passed from the first transceiver to the second computer cluster and the second neighbor identification is passed from the second transceiver toward the first computer cluster. The first neighbor identification is compared with a desired first neighbor identification to establish a first comparison result, and the second neighbor identification is compared with a desired second neighbor identification to establish a second comparison result and a notice is generated.

Abstract: An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.

Abstract: An input/output (I/O) and disk expansion subsystem is provided for an electronics rack which provides expanded I/O and/or disk storage capabilities to electronic subsystems of the rack. The expansion subsystem includes a subsystem enclosure having first and second sides in opposing relation, with the first side accessible through a front of the rack and the second accessible through a back of the rack when the enclosure resides within the rack. A plurality of field-replaceable units reside within the subsystem enclosure, and are accessible and removable through the first or second sides of the enclosure without removing the enclosure from the rack. The field-replaceable units include an input/output adapter cage(s), a storage device cage, power and control supplies, fan assemblies, and a midplane connector assembly. The adapter cage, storage device cage, and power and control supply dock to and are electrically interconnected by the midplane connector assembly.

Abstract: A method, apparatus, and computer program product for load shedding during an emergency power off event. In one embodiment, power is supplied from a main power source to a plurality of electrical loads within a device enclosure. Power loss is detected from the main power source. Upon detecting the power loss, at least one of the electrical loads is disconnected from a supplemental power source such that power to at least one remaining load connected to the supplemental power source is sustained by the supplementary power source.

Abstract: An electronic system enclosure including cooling units to regulate temperature of electrical components therein. In one embodiment, the electronic system enclosure includes field replaceable units which facilitate concurrent maintenance. In this embodiment, air pressure within the electronic system enclosure is maintained while a field replaceable unit is removed. Also in this embodiment, cooling of the remaining electrical components of the electronic system enclosure is continued during removal of a field replaceable unit.

Abstract: An energy management control method and controller reduce power supply current and/or subsystem cooling overhead that reduces system efficiency, may reduce system reliability and may increase ambient noise. Multiple device connectors are supplied from corresponding soft switches that are programmed to provide a current level that is sufficient to supply the maximum current for the device installed in the corresponding device connector. The current level may be determined from device information provided from the device during initialization, which may directly specify a maximum current requirement. Alternatively, the maximum current requirement can be determined from other device-identifying information such as a unique device identifier. As a result a guaranteed maximum current or power and power dissipation can be determined, and multiple power supplies and/or cooling devices such as air movement devices (AMDs) may be enabled, disabled or otherwise controlled accordingly.

Abstract: A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.

Abstract: An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.

Abstract: An addressing model is provided where all resources, including memory and devices, are addressed with internet protocol (IP) addresses. A task, such as an application, may be assigned a range of IP addresses rather than an effective address range. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.

Abstract: A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model abstracts an I/O device such that communication intended for the I/O device may be packetized and sent over a network. Thus, a virtualization platform may packetize communication intended for a remotely located I/O device and transmit the packetized communication over a distance, rather than having to make a call to a library, call a device driver, pin memory, and so forth.

Abstract: A method of validating a configuration of a computer clusters includes transmitting a first neighbor identification to a first flexible service processor (FSP) arranged in the first computer cluster and a second neighbor identification to a second FSP arranged in the second computer cluster, connecting a first end of a cable to a first transceiver arranged in the first cluster and connecting a second end of the cable to a second transceiver arranged in the second cluster. The first neighbor identification is passed from the first transceiver to the second computer cluster and the second neighbor identification is passed from the second transceiver toward the first computer cluster. The first neighbor identification is compared with a desired first neighbor identification to establish a first comparison result, and the second neighbor identification is compared with a desired second neighbor identification to establish a second comparison result and a notice is generated.

Abstract: A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.

Abstract: A method, system, and computer program product are provided for controlling liquid-cooled electronics, which includes measuring a first set point temperature, Ta, wherein the Ta is based on a dew point temperature, Tdp of a computer room. A second set point temperature, Tb, is measured, wherein the Tb is based on a facility chilled liquid inlet temperature, Tci, and a rack power, Prack, of an electronics rack. A Modular Cooling Unit (MCU) set point temperature, Tsp, is selected. The Tsp is the higher value of said Ta and said Tb. Responsive to the selected Tsp, a control valve is regulated. The control valve controls a flow of liquid that passes through a heat exchanger.

Abstract: A method and related apparatus for servicing an electrical/electronic device during power shut offs is provided. The apparatus comprises a service logic having a memory and control component for storing device information during normal device operation and one or more indicators driven by the memory and control component after power shut off to provide service signals. The service logic also includes an auxiliary energy source selectively engageable to provide auxiliary power to the memory and control component during power shut off and to enable providing of service signals through the indicator(s).

Abstract: Systems and methods are provided for cooling an electronics rack, which includes a heat-generating electronics subsystem across which air flows from an air inlet to an air outlet side of the rack. First and second modular cooling units (MCUs) are associated with the rack and configured to provide system coolant to the electronics subsystem for cooling thereof. System coolant supply and return manifolds are in fluid communication with the MCUs for facilitating providing of system coolant to the electronics subsystem, and to an air-to-liquid heat exchanger associated with the rack for cooling air passing through the rack. A controller monitors the system coolant and automatically shuts off flow of system coolant through the heat exchanger, using at least one isolation valve, upon detection of failure at one of the MCUs, while allowing the remaining operational MCU to provide system coolant to the electronics subsystem for liquid cooling thereof.

Abstract: An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.