Abstract: An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.

Abstract: Control of an AC-to-DC power supply assembly fed by a three-phase AC source is provided by: determining whether the power supply assembly includes greater than three single-phase power regulators feeding a common load, with multiple regulators being connected in parallel across a common phase of the AC source, and if so, summing currents provided by the regulators to the common load; and ascertaining whether the summed current is less than a predefined threshold, and if yes, operating the power supply assembly in a line balance mode to maintain power drawn on the phases of the AC source in balance, and if greater than the predefined threshold, operating the power supply assembly in a maximize power mode wherein power is provided to the common load without maintaining power drawn on the phases of the AC source in balance.

Abstract: Systems and methods are provided for cooling an electronics rack and a computer room from a single unit, which includes a heat-generating electronics subsystem across which air flows from an air inlet to an air outlet side of the rack. First and second modular cooling units (MCUs) are associated with the rack and configured to provide system coolant to the electronics subsystem for cooling thereof. System coolant supply and return manifolds are in fluid communication with the MCUs for facilitating providing of system coolant to the electronics subsystem, and to an air-to-liquid heat exchanger associated with the rack for exclusively cooling air passing through the rack, as well as conditioning the ambient air of the computer room. Such cooling is exclusive of an outside-of-rack conditioned air unit.

Abstract: Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.

Abstract: A method for accessing a memory space allocated to a virtual machine, the method includes: receiving a request from the virtual machine to generate, for another virtual machine, a memory credential associated with a certain memory space allocated to the virtual machine; generating, in response to the request, a cryptographically signed credential; sending the cryptographically signed credential to the other virtual machine; receiving from the other virtual machine an access request to access at least one memory entry within the certain memory space; and accessing the at least one memory entry, if the access request complies with the memory credential.

Abstract: An addressing model is provided where all resources, including memory and devices, are addressed with internet protocol (IP) addresses. A task, such as an application, may be assigned a range of IP addresses rather than an effective address range. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.

Abstract: A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model abstracts an I/O device such that communication intended for the I/O device may be packetized and sent over a network. Thus, a virtualization platform may packetize communication intended for a remotely located I/O device and transmit the packetized communication over a distance, rather than having to make a call to a library, call a device driver, pin memory, and so forth.

Abstract: A system and method are provided for implementing a two-tier full-graph interconnect architecture. In order to implement a two-tier full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the two-tier full-graph interconnect architecture. Data is then transmitted from one processor to another within the two-tier full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor chip identifier associated with a target processor to which the data is to be transmitted.

Abstract: An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.

Abstract: A method for supporting low-overhead memory locks within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is ignored. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.

Abstract: Systems and methods are provided for cooling an electronics rack, which includes a heat-generating electronics subsystem across which air flows from an air inlet to an air outlet side of the rack. First and second modular cooling units (MCUs) are associated with the rack and configured to provide system coolant to the electronics subsystem for cooling thereof. System coolant supply and return manifolds are in fluid communication with the MCUs for facilitating providing of system coolant to the electronics subsystem, and to an air-to-liquid heat exchanger associated with the rack for cooling air passing through the rack. A controller monitors the system coolant and automatically shuts off flow of system coolant through the heat exchanger, using at least one isolation valve, upon detection of failure at one of the MCUs, while allowing the remaining operational MCU to provide system coolant to the electronics subsystem for liquid cooling thereof.

Abstract: A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

Abstract: A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

Abstract: Monitoring a plurality of field-replaceable units (FRUs) in an enclosure using two or more microcontroller-equipped power supplies to detect an FRU failure. Upon detection of an FRU failure, a first signal indicative of the failure is communicated from at least one of the microcontroller-equipped power supplies to one or more small computer system interface (SCSI) repeaters over an I2C bus. The one or more SCSI repeaters report a second signal indicative of the failure to one or more central electronics complexes (CECs) over one or more SCSI busses. The first signal may, but need not, be substantially identical to the second signal.

Abstract: A server including a cooling fan assembly and an input/output assembly at opposite ends of the server, and a processor assembly located between the cooling fan assembly and input/output assembly. The server also includes a cover plate that covers the processor assembly and cooling fan assembly and that has a power supply on the face of the cover plate facing the processor assembly and is electrically connected to the processor assembly.

Abstract: A computer chassis is provided that may accommodate direct access storage device cages for various form factors. A 3.5-inch direct access storage device (DASD) cage may support 3.5-inch serial attached SCSI (SAS) direct access storage devices. The 3.5-inch SAS DASD cage includes a DASD backplane with a main connector and eight SAS drive connectors. A SFF direct access storage device cage may support SFF SAS direct access storage devices. The SFF SAS DASD cage may include a DASD backplane with a main connector and two port expanders. The port expanders may support up to twelve SAS DASD with redundant SAS channel wiring and one external 4-channel SAS port.

Abstract: Methods, systems and computer products for SCSI power control, data flow and addressing. Exemplary embodiments include a SCSI system having a SCSI bus with a plurality of data lines, including a first repeater configuration, a second repeater configuration, a method for selectively enabling at least one of the first and second repeater configurations and a method for selectively assigning SCSI IDs on devices on a SCSI bus.

Abstract: A server including a cooling fan assembly and an input/output assembly at opposite ends of the server, and a processor assembly located between the cooling fan assembly and input/output assembly. The server also includes a cover plate that covers the processor assembly and cooling fan assembly and that has a power supply on the face of the cover plate facing the processor assembly and is electrically connected to the processor assembly.

Abstract: Disclosed herein is an engagement system for bulk power assemblies. The system comprising, a first bulk power assembly and a second bulk power assembly having equal numbers of electrical terminals and guide bosses. The system also having a rigid interface member having a first end and a second end, both ends having an equal number of terminal blades as there are electrical terminals on the first bulk power assembly and an equal number of guide blades as there are guide bosses on the first bulk power assembly. The terminal blades being receptive to make an electrical connection with the electrical terminals and the guide blades being receptive to engage with the guide bosses, in response to the interface member being functionally engaged with both bulk power assemblies simultaneously.

Abstract: Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.