Abstract: Subject matter disclosed herein may relate to wireless energy harvesting devices and may relate more particularly to system-on-a-chip testing for wireless energy harvesting devices.

Abstract: This technology includes methods, non-transitory computer readable media, and pattern navigation aiding devices that obtain one or more images of a section of sky. Stars comprising at least one or more artificial stars in the one or more obtained images of the section of the sky that are in an image pattern that match above a set threshold at least one previously shared beacon pattern are identified. Navigational information from the identified image pattern with the at least one or more artificial stars that matches above the set threshold the at least one previously shared beacon pattern is determined and output to provide navigational assistance.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

Abstract: Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit.

Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

Abstract: Disclosed are methods, systems and devices for varying operations of a transponder device based, at least in part, on an availability of energy and/or power that may be harvested and/or collected. In one particular implementation, operations to generate one or more signals from sensor circuitry and/or to perform computations may be varied based, at least in part, on an availability of harvestable and/or collectable energy and/or power.

Abstract: Disclosed are methods, systems and devices for allocating a power signal. In one particular implementation, a reader device may exchange messages with one more transponder devices to determine an allocation of a power signal. For example, one or more transponder devices may provide one or more messages in a downlink signal indicative of a requested signal up time.

Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

Abstract: Disclosed are methods, systems and devices for allocating a power signal. In one particular implementation, a reader device may exchange messages with one more transponder devices to determine an allocation of a power signal. For example, one or more transponder devices may provide one or more messages in a downlink signal indicative of a requested signal up time.

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

Abstract: An electrowetting optical device is provided. The electrowetting optical device includes a first window, a second window, and a cavity disposed between the first window and the second window. The electrowetting optical device additionally includes a first liquid and a second liquid disposed within the cavity, the first liquid and the second liquid substantially immiscible with each other and having different refractive indices such that an interface between the first liquid and the second liquid defines a variable lens. The electrowetting optical device also includes a common electrode in electrical connection with the first liquid and a driving electrode disposed on a sidewall of the cavity and insulated from the first liquid and the second liquid by an insulating polymer dielectric layer. The insulating polymer dielectric layer may be formed using initiated chemical vapor deposition (iCVD).

Abstract: According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.

Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

Abstract: Methods, systems and devices for operation of non-volatile memory device are described herein. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the non-volatile memory element.

Abstract: According to one implementation of the present disclosure, a memory array to block read-access of uninitialized memory locations is disclosed. The memory array includes: a plurality of memory cells apportioned into a plurality of memory columns and a plurality of memory rows, where each of the memory cells is configured to store a single bit of memory data; and one or more initialization columns corresponding to at least one of the plurality of memory columns. The initialization state of a memory row of the memory cells may be configured to be stored in: the memory row; a latch of word-line driver circuitry coupled to the memory array; or a memory cell of the one or more initialization columns of a corresponding row of the plurality of memory rows of the memory array.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.