Patents by Inventor Edward Myers

Edward Myers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CES-BASED LATCHING CIRCUITS
    Publication number: 20180012658
    Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.
    Type: Application
    Filed: September 20, 2017
    Publication date: January 11, 2018
    Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
  • Integrated oscillator circuitry
    Patent number: 9831831
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a comparator stage, a resistor, a capacitor, and active switches arranged to provide a clock signal having a time period that is independent of a first source voltage. Independence may be achieved by using a second source voltage derived from the first source voltage as a fixed ratio.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: November 28, 2017
    Assignee: ARM Limited
    Inventors: Parameshwarappa Anand Kumar Savanth, Shidhartha Das, James Edward Myers, David Michael Bull, Bal S. Sandhu
  • A LIGHT DIFFUSING COMPONENT AND A METHOD OF MANUFACTURING A LIGHT DIFFUSING COMPONENT
    Publication number: 20170336556
    Abstract: A light diffusing component is disclosed. The light diffusing component comprises a substrate, such as glass, having a frontside, a backside spaced apart from the frontside, and an edge configured to receive a light source. The glass sheet includes at least one scattering layer having a plurality of light scattering centers etched into at least a portion of the frontside of the glass sheet. The scattering centers have an increased density as the distance from the edge increases and the scattering centers are randomly distributed in size and smaller than about 200 ?m. Also disclosed is a method of manufacturing a light diffusing component comprising masking a substrate, such as a glass sheet, and etching the substrate such that the density of the resulting scattering centers increased as the distance from the light source increases.
    Type: Application
    Filed: October 21, 2015
    Publication date: November 23, 2017
    Inventors: Michael Etienne, Matthew Wade Fenton, Timothy Edward Myers, Kathleen Ann Wexell
  • LATCHING DEVICE AND METHOD
    Publication number: 20170330618
    Abstract: According to one embodiment of the present disclosure, an apparatus is provided. The apparatus comprises a data input to receive a data signal. The apparatus further comprises a latching circuitry. The latching circuitry comprises a first Correlated Electron Switch (CES) element and a second CES element. The latching circuitry further comprises a control circuit coupled to the first CES element and the second CES element. The control circuit is configured to program impedance states of the first CES element and the second CES element based on the data signal.
    Type: Application
    Filed: July 3, 2017
    Publication date: November 16, 2017
    Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Shidhartha Das
  • Computer-implemented method and computer program for generating a layout of a circuit block of an integrated circuit
    Patent number: 9811625
    Abstract: A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: November 7, 2017
    Assignee: ARM Limited
    Inventor: James Edward Myers
  • Cavity based feature on chip carrier
    Publication number: 20170317036
    Abstract: A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.
    Type: Application
    Filed: April 29, 2017
    Publication date: November 2, 2017
    Inventors: Edward MYERS, Thomas BEMMERL, Melissa STAHL
  • STORAGE BITCELL WITH ISOLATION
    Publication number: 20170294222
    Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Pranay Prabhat, David Walter Flynn, Shidhartha Das, David Michael Bull
  • CES-based latching circuits
    Patent number: 9786370
    Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: October 10, 2017
    Assignee: ARM Ltd.
    Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
  • Photo-patternable gate dielectrics for OFET
    Patent number: 9761817
    Abstract: Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: September 12, 2017
    Assignee: Corning Incorporated
    Inventors: Robert Alan Bellman, Mingqian He, Timothy Edward Myers, Weijun Niu, David Neal Schissel, Kristi Lynn Simonton, Arthur Lawrence Wallace
  • CES-BASED LATCHING CIRCUITS
    Publication number: 20170243621
    Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 24, 2017
    Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
  • Latching device and method
    Patent number: 9734895
    Abstract: According to one embodiment of the present disclosure, an apparatus is provided. The apparatus comprises a data input to receive a data signal. The apparatus further comprises a latching circuitry. The latching circuitry comprises a first Correlated Electron Switch (CES) element and a second CES element. The latching circuitry further comprises a control circuit coupled to the first CES element and the second CES element. The control circuit is configured to program impedance states of the first CES element and the second CES element based on the data signal.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 15, 2017
    Assignee: ARM Ltd.
    Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Shidhartha Das
  • Integrated Oscillator Circuitry
    Publication number: 20170222602
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a comparator stage, a resistor, a capacitor, and active switches arranged to provide a clock signal having a time period that is independent of a first source voltage. Independence may be achieved by using a second source voltage derived from the first source voltage as a fixed ratio.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Parameshwarappa Anand Kumar Savanth, Shidhartha Das, James Edward Myers, David Michael Bull, Bal S. Sandhu
  • Power gating in an electronic device
    Patent number: 9720434
    Abstract: An electronic device 2 has circuitry 4 which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level. A voltage regulator 14 generates the first voltage level VDD1 from a second voltage level VDD2 higher than the first voltage level VDD1. At least one power gate 20, 30 is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 or the reference level. The control signal 22 for the power gate 20, 30 is generated in a second voltage domain supplied with a higher voltage level VDD2 or VDD3 derived from the second voltage level VDD2 supplied to the voltage regulator 14. Hence, an existing high voltage source within the device 2 can be reused for applying a boosted voltage to power gates to improve efficiency of power gating.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 1, 2017
    Assignee: ARM Limited
    Inventors: James Edward Myers, David Walter Flynn, David William Howard
  • HARVESTING POWER FROM AMBIENT ENERGY IN AN ELECTRONIC DEVICE
    Publication number: 20170201099
    Abstract: An electronic device 50 has at least one harvesting unit 52 for harvesting power from ambient energy. At least one circuit 54, including processing circuitry 56, is supplied with power from the harvesting unit 52. Control circuitry 60 is provided to adjust at least one property of the processing circuitry 56 or the at least one harvesting unit 52 to reduce impedance mismatch between an output impedance of the harvesting unit 52 and an input impedance of the at least one circuit 54.
    Type: Application
    Filed: May 11, 2015
    Publication date: July 13, 2017
    Applicant: ARM Limited
    Inventors: Parameshwarappa Anand Kumar SAVANTH, James Edward MYERS, David Walter FLYNN
  • LATCHING DEVICE AND METHOD
    Publication number: 20170178718
    Abstract: According to one embodiment of the present disclosure, an apparatus is provided. The apparatus comprises a data input to receive a data signal. The apparatus further comprises a latching circuitry. The latching circuitry comprises a first Correlated Electron Switch (CES) element and a second CES element. The latching circuitry further comprises a control circuit coupled to the first CES element and the second CES element. The control circuit is configured to program impedance states of the first CES element and the second CES element based on the data signal.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Parameshwarappa Anand Kumar Savanth, James Edward Myers, Shidhartha Das
  • TEST STRUCTURES FOR MANUFACTURING PROCESS OF ORGANIC PHOTO DIODE IMAGING ARRAY
    Publication number: 20170179200
    Abstract: A test structure for characterizing an organic photodiode image sensor includes, on a common substrate, at least one of a cathode sheet resistance portion; a diode capacitance portion; an OPD sheet resistance portion; a contact resistance portion; a step coverage portion; a quantum efficiency portion; a film adhesion portion; and an inkjet printing portion.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 22, 2017
    Inventors: Byung-Kyu Park, Edward Myers, Ick-Hwan Ko, Karthik Nagarajan, Shawn Michael O'Rourke
  • High surface area substrate for cell culture
    Patent number: 9677047
    Abstract: A cell culture microcarrier includes (1) a polystyrene microcarrier base having a remnant of a carboxylic acid group, and (ii) a polypeptide conjugated to the base via the remnant of the carboxylic acid group. The polypeptide may contain a cell adhesive sequence, such as RGD. Cells cultured with such microcarriers exhibit peptide-specific binding to the microcarriers.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: June 13, 2017
    Assignee: Corning Incorporated
    Inventors: Michelle Dawn Fabian, Timothy Edward Myers, Kyle Patrick Snyder, Florence Verrier
  • Anti-glare surface treatment method and articles thereof
    Patent number: 9651720
    Abstract: A glass article including: at least one anti-glare surface having haze, distinctness-of-image, surface roughness, and uniformity properties, as defined herein. A method of making the glass article includes, for example: depositing deformable particles on at least a portion of a glass surface of the article; causing the deposited deformable particles on the surface to deform and adhere to the surface; and contacting the surface having the adhered particles with an etchant to form the anti-glare surface. A display system that incorporates the glass article, as defined herein, is also disclosed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 16, 2017
    Assignee: Corning Incorporated
    Inventors: Charles Warren Lander, Timothy Edward Myers, Kelvin Nguyen, Alan Thomas Stephens, II
  • Device for detecting gases and/or volatile organic compounds (VOC)
    Patent number: 9588084
    Abstract: The present invention concerns a device for detecting gases or volatile organic compounds (VOC) comprising an electrically conducting or semiconducting zone functionalized with an organic film resulting from the polymerization of aromatic diazonium salt derived monomer.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 7, 2017
    Assignees: California Institute of Technology, Commissariat a L'Energie Atomatique Et Aux Energies Alternatives
    Inventors: Guillaume Delapierre, Yanxia Hou-Broutin, Heather McCaig, Edward Myers, Michael L. Roukes
  • Retention control in a memory device
    Patent number: 9542994
    Abstract: A memory device and method of operating the memory device are provided. The memory device has bitcells arranged in a plurality of rows and columns. Row driver circuitry provides access to the array of bitcells by selection of an access row of the plurality of rows. The row driver circuitry comprises a retention control latch to store a retention control value and row power gating circuitry responsive to a retention signal to power gate at least one row when the retention control value has a first value and to leave the at least one row powered when the retention control value has a second value. Row-based retention of the content of the bit cells is thus provided, and the leakage current of the memory device when it is in a retention (e.g. sleep) mode, and only some of its rows contain valid data, can thus be reduced.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: January 10, 2017
    Assignee: ARM Limited
    Inventors: Pranay Prabhat, James Edward Myers