Abstract: Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. A corresponding integrated circuit, printed circuit and method are also provided. These techniques allow the integrated circuit to be used in a variety of contexts, without requiring physical customisation of the integrated circuit to adapt it to its usage context, in particular where connections from the context to the pads of the integrated circuit may be made to individual pads in some contexts or may span more than one pad in other contexts.

Abstract: An article is described herein that includes: a glass, glass-ceramic or ceramic substrate comprising a primary surface; at least one of an optical film and a scratch-resistant film disposed over the primary surface; and an easy-to-clean (ETC) coating comprising a fluorinated material that is disposed over an outer surface of the at least one of an optical film and a scratch-resistant film. The at least one of an optical film and a scratch-resistant film comprises an average hardness of 10 GPa or more. Further, the outer surface of the at least one of an optical film and a scratch-resistant film comprises a surface roughness (Rq) of less than 1.0 nm.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

Abstract: Various implementations described herein refer to a method for providing an integrated circuit with a real-time clock source. The method may include generating a real-time clock signal for the integrated circuit with the real-time clock source. The method may include selectively adjusting clock frequency of the real-time clock signal to save power in the integrated circuit.

Abstract: A data buffer comprises data storage circuitry; input circuitry to input data to be stored by the data storage circuitry at a first operating voltage; output circuitry to output stored data from the data storage circuitry at a second operating voltage different to the first operating voltage; and control circuitry to control an operating voltage of the data storage circuitry to be substantially the first operating voltage during a data input operation by the input circuitry and to be substantially the second operating voltage during a data output operation by the output circuitry.

Abstract: A backlight unit for use with an LCD display device (10), the backlight unit (24), including a cured polymer layer (34), disposed on a major surface of the glass substrate (28), the cured polymer layer (34) exhibiting a pencil hardness value of 1 H-2 H as measured in accordance with ASTM D3363-05 and an adhesion of 5 B as measured in accordance with ASTM D3359-09. A maximum color shift (Delta) ymax of the cured polymer layer (34) is less than about 0.015 after aging for 1000 hours at 60° C. and 90% relative humidity.

Abstract: An article that includes: a glass, glass-ceramic or ceramic substrate comprising a primary surface; at least one of an optical film and a scratch-resistant film disposed over the primary surface; and an easy-to-clean (ETC) coating comprising a fluorinated material that is disposed over an outer surface of the at least one of an optical film and a scratch-resistant film. The at least one of an optical film and a scratch-resistant film comprises an average hardness of 12 GPa or more. Further, the outer surface of the at least one of an optical film and a scratch-resistant film comprises a surface roughness (Rq) of less than 1.0 nm. Further, the at least one of an optical film and a scratch-resistant film comprises a total thickness of about 500 nm or more.

Abstract: A device comprising a storage array, the storage array comprising a first signal line and a second signal line, at least one correlated electron switch in electrical communication with the first signal line and the second signal line, and control circuitry for driving the correlated electron switch with at least one programming signal.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

Abstract: Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.

Abstract: An electronic device 50 has at least one harvesting unit 52 for harvesting power from ambient energy. At least one circuit 54, including processing circuitry 56, is supplied with power from the harvesting unit 52. Control circuitry 60 is provided to adjust at least one property of the processing circuitry 56 or the at least one harvesting unit 52 to reduce impedance mismatch between an output impedance of the harvesting unit 52 and an input impedance of the at least one circuit 54.

Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power.

Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage.

Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.