Abstract: A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the correlated electron element.

Abstract: A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states; a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.

Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

Abstract: Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit.

Abstract: Various implementations described herein are directed to an integrated circuit having a core array region with an array of memory devices. The integrated circuit may include a periphery region having periphery logic devices that interface with the array of memory devices. The integrated circuit may include a boundary region having one or more buffer devices coupled to body terminals of the periphery logic devices to drive the body terminals of the periphery logic devices using a body biasing signal provided by the one or more buffer devices.

Abstract: An interface device for a data processing system is provided. The interface device comprises first interface circuitry to receive incoming data and second interface circuitry to transmit processed data to a data store for storage. The interface device is provided with processing circuitry to generate the processed data from the incoming data wherein the processing carried out reduces the data in size. The processing circuitry is also responsive to at least one characteristic of the incoming data or the processed data to transmit a notification signal to a data processing component of the data processing system.

Abstract: Methods, systems, and devices supporting unregulated voltage stacked memory are described. A memory device may include one or more memory cells used to store information (e.g., in the form of a logic state) and configured into a number of memory banks. In some embodiments, the memory cells may be stacked. The memory device may also include multiple power supplies, which may be arranged in a series configuration between the memory banks. A memory control logic may be coupled in series with the power supplies and configured to equalize power across stacked memory cells when performing a read operation or a write operation to any of the plurality of stacked memory cells.

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.

Abstract: A data buffer comprises data storage circuitry; input circuitry to input data to be stored by the data storage circuitry at a first operating voltage; output circuitry to output stored data from the data storage circuitry at a second operating voltage different to the first operating voltage; and control circuitry to control an operating voltage of the data storage circuitry to be substantially the first operating voltage during a data input operation by the input circuitry and to be substantially the second operating voltage during a data output operation by the output circuitry.

Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.

Abstract: A method, system and surface covering for enabling wireless detection of damage to a structure is disclosed. At least one array having a plurality of nodes are coupled to a surface covering, such as at least one of a wall, ceiling and floor covering for a least a portion of the structure. An electronic reader is operable to wirelessly interrogate the array and read return signals from nodes in the array. The return signals contain data representing an ID for corresponding responsive nodes in the array, and the returned IDs are extracted and compared to a plurality of IDs stored in a data store for nodes in any given array. A mismatch between the returned and stored IDs for the nodes in the array indicates a structural defect in a respective portion of the structure overlaid by the floor/wall covering.

Abstract: A light diffusing component is disclosed. The light diffusing component comprises a substrate, such as glass, having a frontside, a backside spaced apart from the frontside, and an edge configured to receive a light source. The glass sheet includes at least one scattering layer having a plurality of light scattering centers etched into at least a portion of the frontside of the glass sheet. The scattering centers have an increased density as the distance from the edge increases and the scattering centers are randomly distributed in size and smaller than about 200 ?m. Also disclosed is a method of manufacturing a light diffusing component comprising masking a substrate, such as a glass sheet, and etching the substrate such that the density of the resulting scattering centers increased as the distance from the light source increases.

Abstract: A glass article comprising a first surface and an opposing second surface, wherein the first surface comprises a plurality of light extraction features (220), ones of the plurality of light extraction features (220) having scattering particles and binder material, wherein the plurality of light extraction features produces a color shift Ay<0.01 per 500 mm of length, and wherein a difference in Fresnel reflections at the first surface at 45 degrees measured within the respective glass article at 450 nm and 630 nm is less than 0.015%. A light extracting ink is also provided comprising scattering particles and a binder material, wherein Fresnel reflections between the binder material and an adjacent substrate are substantially invariant with respect to wavelength. A light extracting ink is also provided comprising scattering particles and a binder material, wherein the binder material has an index of refraction equal to that of an adjacent substrate at a single wavelength.

Abstract: Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

Abstract: Various implementations described herein are directed to an integrated circuit for brown-out detection. The integrated circuit may include a first stage configured to receive an input voltage and provide a first voltage independent of temperature while remaining related to the input voltage. The integrated circuit may include a second stage configured to receive the input voltage, receive the first voltage from the first stage, and up-convert the first voltage as input voltage lowers. The second stage may be configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage. The integrated circuit may include a third stage configured to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

Abstract: Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.

Abstract: A gas analysis system includes a fluidic channel for flow of a gas to be analyzed, a detector in the channel and adapted for measuring interactions of the gas with the detector, the detector including a resonator of the electromechanical nanosystem (NEMS) type and a heating system for heating a part of the detector, an actuation device for vibrationally actuating the resonator according to an excitation signal applied to an input of the detector, a detection device adapted for providing an output electric signal representative of the vibrations of the resonator, a read-out device connected to an input of the detector and configured for simultaneously measuring, from the output signal of the detector, the change in resonance frequency and the change in amplitude of the vibrations at the resonance frequency of the resonator, and a processing device configured for determining from the changes a fluidic characteristic of the gas.

Abstract: A device comprising a storage array, the storage array comprising a first signal line and a second signal line, at least one correlated electron switch in electrical communication with the first signal line and the second signal line, and control circuitry for driving the correlated electron switch with at least one programming signal.