Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature.

Abstract: A sensor for detecting analytes, a method of making the sensor, and a method of using the sensor. In one embodiment, the present invention comprises at least one array comprising a plurality of resonators. The resonators can be arranged in a plurality of rows and a plurality of columns, and can be connected in a combined series-parallel configuration. The resonators can be adapted to vibrate independently at about the same resonance frequency and about the same phase. The sensor can also comprise an actuator and a signal detector electrically coupled to the array. The sensor can also further comprise an analyte delivery system and can be functionalized for detection of at least one analyte.

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract: An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry.

Abstract: An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry.

Abstract: An integrated circuit 2 comprises a functional circuit 4, 6 which is arranged to operate in response to an operational clock signal having an operational clock frequency. To conserve power, the clock signal is distributed across the integrated circuit 2 at a distribution clock frequency which is less than the operational clock frequency. A clock converter 10 is provided to convert the distribution clock signal into the operational clock signal for controlling operation of the functional circuit 4, 6.

Abstract: A linear actuator includes a housing and a cover tube that is supported relative to the housing. A nut engages the cover tube so as to prevent rotation of the nut relative to the cover tube. A lead screw rotatably engages the nut, wherein rotation of the lead screw causes the nut to travel along the lead screw.

Abstract: A method of making an article having a textured glass surface, including, for example: attaching microencapsulated particles to a portion of a glass surface of the article; and contacting the glass surface having the attached microencapsulated particles with an etchant to form the textured surface. A glass article prepared by the method including: at least one textured surface having excellent haze, distinctness-of-image, surface roughness, and uniformity properties, as defined herein. A display system that incorporates the glass article, as defined herein, is also disclosed.

Abstract: A glass etching medium and a method for etching the surface of a glass sheet to modify surface flaw characteristics without degrading the optical quality of the sheet surface, wherein the etching medium is a thickened aqueous acidic fluoride-containing paste comprising at least one dissolved, water-soluble, high-molecular-weight poly (ethylene oxide) polymer thickener.

Abstract: An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free.

Abstract: A monitoring circuit for an integrated circuit comprises a non-temperature-inverted circuit and a temperature-inverted circuit. Operating parameters of the two circuits are measured, representing the propagation speed of signals in the respective circuits. In response to a change in temperature, the non-temperature-inverted circuit slows down and the temperature-inverted circuit speeds up. In contrast, in response to a change in operating voltage both circuits either speed up or slow down. This divergence in response to temperature and similar response to voltage enables the monitoring circuit to distinguish between changes in operating voltage and changes in operating temperature.

Abstract: An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry.

Abstract: An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell.

Abstract: Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.

Abstract: A clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The circuitry receives a clock signal, a clock enable signal having either an enable value or a disable value, and a power mode signal having either a low power value (indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down), or a functional mode value (indicating the plurality of synchronous elements are to be powered). A clock gating unit has logic circuitry that is configured to output the clock signal or the predetermined gated value depending upon the low power value and the functional mode value.

Abstract: The present invention concerns a device for detecting gases or volatile organic compounds (VOC) comprising an electrically conducting or semiconducting zone f unctionalized with an organic film resulting from the polymerization of aromatic diazonium salt derived monomer.

Abstract: An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry.

Abstract: A monitoring circuit 14, 16, 18, 20, 22 for monitoring an operating parameter of an integrated circuit 2 comprises a ring oscillator circuit 80 comprising a plurality of serially connected inverting stages 82-1, 82-2, 82-3. At least one of the inverting stages 82-1, 82-2 comprises at least one leakage transistor 64-1, 64-2 which is configured to operate in a leakage mode in which substantially all current through the at least one leakage transistor is a leakage current, and a capacitive element 70-1 arranged to be charged or discharged in dependence on the leakage current. The ring oscillator circuit 80 thus generates an oscillating signal with an oscillation period dependent on a rate at which the capacitive element 70-1 is charged or discharged. The operating parameter controls a magnitude of the leakage current so that the oscillation period indicates the operating parameter.

Abstract: A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value.