Abstract: Various implementations described herein are directed to an integrated circuit for brown-out detection. The integrated circuit may include a first stage configured to receive an input voltage and provide a first voltage independent of temperature while remaining related to the input voltage. The integrated circuit may include a second stage configured to receive the input voltage, receive the first voltage from the first stage, and up-convert the first voltage as input voltage lowers. The second stage may be configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage. The integrated circuit may include a third stage configured to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: A computer implemented method and a computer program for generating a layout of a circuit block of an integrated circuit are provided. Input data is received identifying a plurality of circuit elements and interconnections required to implement the circuit block, and the method also has access to a cell library providing a plurality of standard cells, where each standard cell defines a corresponding circuit element using transistors, the transistors comprising n-type transistors and p-type transistors. A plurality of rows are formed within which to place standard cells from the cell library in order to implement the circuit block, the plurality of rows including at least one body biased row in which a body bias is to be applied in respect of either the n-type transistors or the p-type transistors provided by the standard cells placed in that body biased row.

Abstract: A linear actuator includes a housing and a cover tube that is supported relative to the housing. A nut engages the cover tube so as to prevent rotation of the nut relative to the cover tube. A lead screw rotatably engages the nut, wherein rotation of the lead screw causes the nut to travel along the lead screw.

Abstract: Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.

Abstract: Mechanisms are provided for energy management signalling with an apparatus for processing data, such as a system-on-chip integrated circuit (2). Processing circuitry (6, 8, 10) is coupled to consumer energy interface circuitry (14, 16, 18) which communicates with energy management circuitry (4). The energy management signals which are communicated include a static power consumption signal indicative of a level of power consumption which is independent of processing operations being performed and a dynamic power consumption signal indicative of a level of dynamic power consumption which is dependent upon the processing operations being performed.

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: A method of making an article having a textured glass surface, including, for example: attaching microencapsulated particles to a portion of a glass surface of the article; and contacting the glass surface having the attached microencapsulated particles with an etchant to form the textured surface. A glass article prepared by the method including: at least one textured surface having excellent haze, distinctness-of-image, surface roughness, and uniformity properties, as defined herein. A display system that incorporates the glass article, as defined herein, is also disclosed.

Abstract: A sensor for detecting analytes, a method of making the sensor, and a method of using the sensor. In one embodiment, the present invention comprises at least one array comprising a plurality of resonators. The resonators can be arranged in a plurality of rows and a plurality of columns, and can be connected in a combined series-parallel configuration. The resonators can be adapted to vibrate independently at about the same resonance frequency and about the same phase. The sensor can also comprise an actuator and a signal detector electrically coupled to the array. The sensor can also further comprise an analyte delivery system and can be functionalized for detection of at least one analyte.

Abstract: An electronic device 2 has circuitry 4 which operates in a first voltage domain 6 supplied with a first voltage level VDD1 and a reference voltage level. A voltage regulator 14 generates the first voltage level VDD1 from a second voltage level VDD2 higher than the first voltage level VDD1. At least one power gate 20, 30 is provided for selectively coupling the circuitry 4 to one of the first voltage level VDD1 or the reference level. The control signal 22 for the power gate 20, 30 is generated in a second voltage domain supplied with a higher voltage level VDD2 or VDD3 derived from the second voltage level VDD2 supplied to the voltage regulator 14. Hence, an existing high voltage source within the device 2 can be reused for applying a boosted voltage to power gates to improve efficiency of power gating.

Abstract: A gas analysis system includes a fluidic channel for flow of a gas to be analyzed, a detector in the channel and adapted for measuring interactions of the gas with the detector, the detector including a resonator of the electromechanical nanosystem (NEMS) type and a heating system for heating a part of the detector, an actuation device for vibrationally actuating the resonator according to an excitation signal applied to an input of the detector, a detection device adapted for providing an output electric signal representative of the vibrations of the resonator, a read-out device connected to an input of the detector and configured for simultaneously measuring, from the output signal of the detector, the change in resonance frequency and the change in amplitude of the vibrations at the resonance frequency of the resonator, and a processing device configured for determining from the changes a fluidic characteristic of the gas.

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: A glass article including: at least one anti-glare surface having haze, distinctness-of-image, surface roughness, and uniformity properties, as defined herein. A method of making the glass article includes, for example: depositing deformable particles on at least a portion of a glass surface of the article; causing the deposited deformable particles on the surface to deform and adhere to the surface; and contacting the surface having the adhered particles with an etchant to form the anti-glare surface. A display system that incorporates the glass article, as defined herein, is also disclosed.

Abstract: A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature.

Abstract: A glass article including: at least one anti-glare surface having haze, distinctness-of-image, surface roughness, and uniformity properties, as defined herein. A method of making the glass article includes, for example: depositing deformable particles on at least a portion of a glass surface of the article; causing the deposited deformable particles on the surface to deform and adhere to the surface; and contacting the surface having the adhered particles with an etchant to form the anti-glare surface. A display system that incorporates the glass article, as defined herein, is also disclosed.

Abstract: A nano electro-mechanical system (NEMS) formed on a substrate is provided including at least one fixed part associated with the substrate and at least one movable part in relation to the substrate, the system including a transduction component configured to excite the movable part to confer on it a movement and/or to detect a movement of the movable part, the transduction component including at least one electrically conductive material. The electrically conductive material is made of an AlSi alloy based deposition, the deposition being supported at least in part by the movable part of the system.

Abstract: Described herein are coating compositions for protecting one-glass solution (OGS) glasses and other display glasses during processing. The coatings are non-reactive to typical indium-tin oxide touch components, metal electrodes, and black matrix inks, and can thus be used to over-coat these materials. In one aspect, the coating compositions described herein can be applied by a screen printing application process in a single layer or in multiple layers and are compatible with CNC edge grinding and acid etching. Further, the protective coatings are rigid, but not brittle, and are durable but still able to be processed rapidly. Additionally, the protective coatings are transparent, allowing alignment marks on the substrates to be visible. Finally, the protective coatings can easily be removed after substrate processing has been completed.

Abstract: An integrated circuit 6 including a first voltage domain 4 incorporates real time clock circuitry 12 that communicates via communication circuitry 18 with processing circuitry 16 contained within a second voltage domain. The communication circuitry 18 includes first parallel-to-serial conversion circuitry 24 located within the first voltage domain 4, level shifting circuitry 32 for passing serial signals between the voltage domains and second parallel-to-serial circuitry 26 located in the second voltage domain.

Abstract: A glass etching medium and a method for etching the surface of a glass sheet to modify surface flaw characteristics without degrading the optical quality of the sheet surface, wherein the etching medium is a thickened aqueous acidic fluoride-containing paste comprising at least one dissolved, water-soluble, high-molecular-weight poly (ethylene oxide) polymer thickener.

Abstract: A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device.