Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR
    Publication number: 20140129808
    Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
    Type: Application
    Filed: April 27, 2012
    Publication date: May 8, 2014
    Inventors: Alon Naveh, Yuval Yosef, Eliezer Weissmann, Anil Aggarwal, Efraim Rotem, Avi Mendelson, Ronny Ronen, Boris Ginzburg, Michael Mishaeli, Scott D. Hahn, David A. Koufaty, Ganapati Srinivasa, Guy Therien
  • OPERATING POINT MANAGEMENT IN MULTI-CORE ARCHITECTURES
    Publication number: 20140115362
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2013
    Publication date: April 24, 2014
    Inventors: Efraim ROTEM, Oren LAMDAN, Alon NAVEH
  • DYNAMICALLY ALLOCATING A POWER BUDGET OVER MULTIPLE DOMAINS OF A PROCESSOR
    Publication number: 20140115351
    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nadav Shulman
  • Deterministic management of dynamic thermal response of processors
    Patent number: 8707060
    Abstract: Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Doron Rajwan, Lev Finkelstein
  • Controlling Power Consumption By Power Management Link
    Publication number: 20140095911
    Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Inventors: Nir Rosenzweig, Efraim Rotem, Jawad Haj-Yihia, Ohad Falik
  • Computing System and Processor With Fast Power Surge Detection And Instruction Throttle Down To Provide For Low Cost Power Supply Unit
    Publication number: 20140095905
    Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Krishnakanth Sistla, Martin Mark Rowland, Efraim Rotem, Brian J. Griffith, Ankush Varma, Anupama Suryanarayanan
  • PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM
    Publication number: 20140082630
    Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.
    Type: Application
    Filed: December 30, 2011
    Publication date: March 20, 2014
    Inventors: Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli, Alon Naveh, David A. Koufaty, Scott D. Hahn, Tong Li, Avi Mendleson, Eugene Gorbatov, Hisham Abu-Salah, Dheeraj R. Subbareddy, Paolo Narvaez, Aamer Jaleel, Efraim Rotem, Yuval Yosef, Anil Aggarwal, Kenzo Van Craeynest
  • Method and apparatus to control power consumption of a plurality of processor cores
    Patent number: 8650424
    Abstract: For one disclosed embodiment, a plurality of processor cores of a multicore processor may be operated at variable performance levels. One processor core may operate at a performance level different than a performance level at which another processor core may operate. Performance levels of multiple processor cores may be identified. Power consumption of the plurality of processor cores may be controlled based at least in part on the identified performance levels. Other embodiments are also disclosed.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: February 11, 2014
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Oren Lamdan, Alon Naveh
  • METHOD AND APPARATUS OF POWER MANAGMENT OF PROCESSOR
    Publication number: 20140040643
    Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
    Type: Application
    Filed: May 14, 2013
    Publication date: February 6, 2014
    Inventors: Efraim Rotem, Barnes Cooper, Guy Therien, Eliezer Weissmann, Anil Aggarwal
  • EFFICIENT INTEGRATED SWITCHING VOLTAGE REGULATOR
    Publication number: 20140006808
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • Extension of CPU Context-State Management for Micro-Architecture State
    Publication number: 20140006758
    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Michael Mishaeli, Boris Ginzburg, Alon Naveh
  • COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT
    Publication number: 20130283032
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 24, 2013
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem
  • COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT
    Publication number: 20130275737
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 17, 2013
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT
    Publication number: 20130275796
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 17, 2013
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • Apparatus and method for high current protection
    Patent number: 8539269
    Abstract: An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Avinash N. Ananthakrishnan, Doron Rajwan, Kosta Luria, Ronny Korner, Dan Baum
  • Metrology Systems and Methods
    Publication number: 20130229661
    Abstract: Various metrology systems and methods are provided. One metrology system includes a light source configured to produce a diffraction-limited light beam, an apodizer configured to shape the light beam in the entrance pupil of illumination optics, and optical elements configured to direct the diffraction-limited light beam from the apodizer to an illumination spot on a grating target on a wafer and to collect scattered light from the grating target. The metrology system further includes a field stop and a detector configured to detect the scattered light that passes through the field stop. In addition, the metrology system includes a computer system configured to determine a characteristic of the grating target using output of the detector.
    Type: Application
    Filed: April 17, 2013
    Publication date: September 5, 2013
    Applicant: KLA-Tencor Corporation
    Inventors: Daniel Kandel, Vladimir Levinski, Alexander Svizher, Joel Seligson, Andrew Hill, Ohad Bachar, Amnon Manassen, Yung-Ho Alex Chuang, Ilan Sela, Moshe Markowitz, Daria Negri, Efraim Rotem
  • MANAGING POWER CONSUMPTION IN A MULTI-CORE PROCESSOR
    Publication number: 20130232368
    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 5, 2013
    Inventors: ERIC FETZER, REID RIEDLINGER, DON SOLTIS, WILLIAM BOWHILL, SATISH SHRIMALI, KRISHNAKANTH SISTLA, EFRAIM ROTEM, RAKESH KUMAR, VIVEK GARG, ALON NAVEH, LOKESH SHARMA
  • POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES
    Publication number: 20130219196
    Abstract: Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 19, 2013
    Publication date: August 22, 2013
    Inventors: Lev Finkelstein, Efraim Rotem, Aviad Cohen, Ronny Ronen, Doron Rajwan
  • Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor
    Publication number: 20130179709
    Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2013
    Publication date: July 11, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Jeremy J. Shrall, Eric C. Samson, Eliezer Wiessmann, Ryan Wells
  • User Level Control Of Power Management Policies
    Publication number: 20130179706
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2013
    Publication date: July 11, 2013
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt