Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTROLLING A GUARANTEED FREQUENCY OF A PROCESSOR
    Publication number: 20160147275
    Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Eliezer Weissmann, Hisham Abu Salah, Efraim Rotem, Guy M. Therien, Nadav Shulman, Esfir Natanzon, Paul S. Diefenbaugh
  • Mapping a performance request to an operating frequency in a processor
    Patent number: 9348401
    Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Paul Diefenbaugh, Guy Therien, Nir Rosenzweig
  • Apparatus and method for controlling the reliability stress rate on a processor
    Patent number: 9317389
    Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 19, 2016
    Assignee: INTEL CORPORATION
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Nadav Shulman, Shmulik Zobel, Allen Chu
  • Controlling a turbo mode frequency of a processor
    Patent number: 9292068
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells, Nadav Shulman
  • Method and apparatus to protect a processor against excessive power usage
    Patent number: 9292362
    Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Lev Makovsky, Zeev Sperber, Efraim Rotem, Nir Rosenzweig, Stanislav Shwartsman, Raanan Sade, Igor Yanover, Gavri Berger, Tomer Weiner, Ron Gabor
  • OPTIMIZATION OF ENERGY USAGE IN A PROCESSOR
    Publication number: 20160077569
    Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Yoni Aizik, Eliezer Weissmann, Efraim Rotem, Yevgeni Sabin, Doron Rajwan, Ahmad Yasin
  • Providing Lifetime Statistical Information For A Processor
    Publication number: 20160070321
    Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 10, 2016
    Inventors: Dorit Shapira, Efraim Rotem, Doron Rajwan, Nadav Shulman, Esfir Natanzon, Nir Rosenzweig
  • Techniques and system for managing platform temperature
    Patent number: 9268378
    Abstract: In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 23, 2016
    Assignee: INTEL CORPORATION
    Inventors: Efraim Rotem, Alon Naveh, Doron Rajwan, Nadav Shulman, Eliezer Weissmann
  • Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor
    Publication number: 20160026229
    Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
    Type: Application
    Filed: October 6, 2015
    Publication date: January 28, 2016
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Jeremy J. Shrall, Eric C. Samson, Eliezer Weissmann, Ryan Wells
  • METHOD AND APPARATUS FOR SELECTING AN INTERCONNECT FREQUENCY IN A COMPUTING SYSTEM
    Publication number: 20160026479
    Abstract: In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 28, 2016
    Inventors: Nir Rosenzweig, Efraim Rotem, Doron Rajwan, Nadav Shulman, Eliezer Weissmann
  • OPERATING POINT MANAGEMENT IN MULTl-CORE ARCHITECTURES
    Publication number: 20160018882
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.
    Type: Application
    Filed: September 26, 2015
    Publication date: January 21, 2016
    Inventors: EFRAIM ROTEM, OREN LAMDAN, ALON NAVEH
  • Dynamically Controlling Cache Size To Maximize Energy Efficiency
    Publication number: 20160011975
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2015
    Publication date: January 14, 2016
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Controlling temperature of multiple domains of a multi-domain processor using a cross-domain margin
    Patent number: 9235254
    Abstract: In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Tomer Ziv, Doron Rajwan, Efraim Rotem
  • AUTONOMOUS C-STATE ALGORITHM AND COMPUTATIONAL ENGINE ALIGNMENT FOR IMPROVED PROCESSOR POWER EFFICIENCY
    Publication number: 20160004296
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: Intel Corporation
    Inventors: JAWADH HAJ-YIHIA, ELIEZER WEISSMANN, VIJAY S R DEGALAHAL, NADAV SHULMAN, TAL KUZI, ITAY FRANKO, AMIT GUR, EFRAIM ROTEM
  • User Level Control Of Power Management Policies
    Publication number: 20160004291
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • METHOD AND APPARATUS FOR DETERMINING THREAD EXECUTION PARALLELISM
    Publication number: 20150379668
    Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: ELIEZER WEISSMANN, ARIK GIHON, EFRAIM ROTEM, PAUL S. DIEFENBAUGH, ERIC C. SAMSON, MICHAEL MISHAELI, YONI AIZIK, CHEN RANEL
  • APPARATUS AND METHOD FOR A USER CONFIGURABLE RELIABILITY CONTROL LOOP
    Publication number: 20150377955
    Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Eric Distefano, James G. Hermerding, II, Esfir Natanzon
  • ENHANCING POWER-PERFORMANCE EFFICIENCY IN A COMPUTER SYSTEM
    Publication number: 20150370304
    Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.
    Type: Application
    Filed: June 24, 2014
    Publication date: December 24, 2015
    Inventors: HISHAM ABU SALAH, ELIEZER WEISSMANN, EFRAIM ROTEM, PAUL S. DIEFENBAUGH, JAY D. SCHWARTZ, SHARAD C. TRIPATHI
  • Forcing A Processor Into A Low Power State
    Publication number: 20150355705
    Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
  • Controlling operating frequency of a core domain based on operating condition of a non-core domain of a multi-domain processor
    Patent number: 9176565
    Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Jeremy J. Shrall, Eric C. Samson, Eliezer Weissmann, Ryan Wells