Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • User level control of power management policies
    Patent number: 9170624
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Optics symmetrization for metrology
    Patent number: 9164397
    Abstract: The present invention includes an illumination source, at least one illumination symmetrization module (ISM) configured to symmetrize at least a portion of light emanating from the illumination source, a first beam splitter configured to direct a first portion of light processed by the ISM along an object path to a surface of one or more specimens and a second portion of light processed by the ISM along a reference path, and a detector disposed along a primary optical axis, wherein the detector is configured to collect a portion of light reflected from the surface of the one or more specimens.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: October 20, 2015
    Assignee: KLA-Tencor Corporation
    Inventors: Amnon Manassen, Daniel Kandel, Moshe Baruch, Joel L. Seligson, Alexander Svizher, Guy Cohen, Efraim Rotem, Ohad Bachar, Daria Negri, Noam Sapiens
  • Dynamically controlling cache size to maximize energy efficiency
    Patent number: 9158693
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode
    Patent number: 9122464
    Abstract: Embodiments of the invention relate to energy efficient and conserving thermal throttling of electronic device processors using a zero voltage processor state. For example, a processor die may include a power control unit (PCU), and an execution unit having power gates and a thermal sensor. The PCU is attached to the thermal sensor to determine if a temperature of the execution unit has increased to greater than an upper threshold, such as while the execution unit is processing data in an active processor power state. The PCU is also attached to the power gates so that upon such detection, it can change the active processor power state to a zero processor power state to reduce the temperature of the execution unit. When the sensor detects that the temperature has decreased to less than a lower threshold, the PCU can change the processor power state back to the active state.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Inder M. Sodhi, Efraim Rotem, Alon Naveh, Sanjeev S. Jahagirdar, Varghese George
  • User level control of power management policies
    Patent number: 9098261
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Determining an effective stress level on a processor
    Patent number: 9098561
    Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Dorit Shapira, Efraim Rotem, Douglas R. Moran
  • Controlling current transients in a processor
    Patent number: 9092210
    Abstract: In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: July 28, 2015
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Alon Naveh, Eliezer Weissmann, Michael Zelikson
  • Metrology systems and methods
    Patent number: 9080971
    Abstract: Various metrology systems and methods are provided. One metrology system includes a light source configured to produce a diffraction-limited light beam, an apodizer configured to shape the light beam in the entrance pupil of illumination optics, and optical elements configured to direct the diffraction-limited light beam from the apodizer to an illumination spot on a grating target on a wafer and to collect scattered light from the grating target. The metrology system further includes a field stop and a detector configured to detect the scattered light that passes through the field stop. In addition, the metrology system includes a computer system configured to determine a characteristic of the grating target using output of the detector.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: July 14, 2015
    Assignee: KLA-Tencor Corp.
    Inventors: Daniel Kandel, Vladimir Levinski, Alexander Svizher, Joel Seligson, Andrew Hill, Ohad Bachar, Amnon Manassen, Yung-Ho Alex Chuang, Ilan Sela, Moshe Markowitz, Daria Negri, Efraim Rotem
  • Dynamically allocating a power budget over multiple domains of a processor
    Patent number: 9081557
    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: July 14, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nadav Shulman
  • Estimating temperature of a processor core in a low power state without thermal sensor information
    Patent number: 9074947
    Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan, Nadav Shulman, Alon Naveh
  • Managing power consumption in a multi-core processor
    Patent number: 9075614
    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Eric Fetzer, Reid Riedlinger, Don Soltis, William Bowhill, Satish Shrimali, Krishnakanth Sistla, Efraim Rotem, Rakesh Kumar, Vivek Garg, Alon Naveh, Lokesh Sharma
  • Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation
    Patent number: 9075610
    Abstract: An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Avinash N. Ananthakrishnan, Alon Naveh, Hisham Abu Salah, Nadav Shulman
  • Managing power consumption in a multi-core processor
    Patent number: 9069555
    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the dynamic capacitance of the processor such that the dynamic capacitance is within an allowable dynamic capacitance value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Eric Fetzer, Reid J. Reidlinger, Don Soltis, William J. Bowhill, Satish Shrimali, Krishnakanth Sistla, Efraim Rotem, Rakesh Kumar, Vivek Garg, Alon Naveh, Lokesh Sharma
  • EFFICIENT INTEGRATED SWITCHING VOLTAGE REGULATOR
    Publication number: 20150169025
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 18, 2015
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • Techniques to manage operational parameters for a processor
    Patent number: 9032223
    Abstract: Techniques to manage operational parameters for a processor are described. For instance, a method includes monitoring performance values representing physical characteristics for multiple components of a computing platform, and managing a performance level for a processor based on the performance values and one or more operational parameters for the processor. The operational parameters may include one or more transitory operational parameters that cause the processor to temporarily exceed operational parameters set by a thermal design power limit. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: May 12, 2015
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eric Distefano, Jim Hermerding, Ronny Korner, Yuval Yosef
  • Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor
    Patent number: 9026815
    Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Jeremy J. Shrall, Eric C. Samson, Eliezer Wiessmann, Ryan Wells
  • Efficient integrated switching voltage regulator comprising switches coupled to bridge drivers to provide regulated power supply to power domains
    Patent number: 9003209
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • ENERGY MONITOR FOR A POWER SOURCE
    Publication number: 20150091550
    Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: EFRAIM ROTEM, NIR ROSENZWEIG, JEFFREY A. CARLSON, PHILIP R. LEHWALDER, NADAV SHULMAN, DORON RAJWAN
  • Controlling A Turbo Mode Frequency Of A Processor
    Publication number: 20150095673
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 2, 2015
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Wiessmann, Ryan Wells, Nadav Shulman
  • Controlling temperature of multiple domains of a multi-domain processor using a cross domain margin
    Patent number: 8954770
    Abstract: In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishan, Tomer Ziv, Doron Rajwan, Efraim Rotem