Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metrology Systems and Methods
    Publication number: 20150036142
    Abstract: Various metrology systems and methods are provided. One metrology system includes a light source configured to produce a diffraction-limited light beam, an apodizer configured to shape the light beam in the entrance pupil of illumination optics, and optical elements configured to direct the diffraction-limited light beam from the apodizer to an illumination spot on a grating target on a wafer and to collect scattered light from the grating target. The metrology system further includes a field stop and a detector configured to detect the scattered light that passes through the field stop. In addition, the metrology system includes a computer system configured to determine a characteristic of the grating target using output of the detector.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Daniel Kandel, Vladimir Levinski, Alexander Svizher, Joel Seligson, Andrew Hill, Ohad Bachar, Amnon Manassen, Yung-Ho Alex Chuang, Ilan Sela, Moshe Markowitz, Daria Negri, Efraim Rotem
  • Controlling a turbo mode frequency of a processor
    Patent number: 8943340
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: January 27, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Wiessman, Ryan Wells, Nadav Shulman
  • TECHNIQUES AND SYSTEM FOR MANAGING PLATFORM TEMPERATURE
    Publication number: 20150006937
    Abstract: In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: EFRAIM ROTEM, ALON NAVEH, DORON RAJWAN, NADAV SHULMAN, ELIEZER WEISSMANN
  • Apparatus And Method To Track Device Usage
    Publication number: 20150006829
    Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: DORON RAJWAN, NADAV SHULMAN, DORIT SHAPIRA, KOSTA LURIA, EFRAIM ROTEM
  • APPARATUS AND METHOD FOR CONTROLLING THE RELIABILITY STRESS RATE ON A PROCESSOR
    Publication number: 20150006971
    Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Nadav Shulman, Shmulik Zobel, Allen Chu
  • Method And Apparatus To Protect A Processor Against Excessive Power Usage
    Publication number: 20140380338
    Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: LEV MAKOVSKY, ZEEV SPERBER, EFRAIM ROTEM, NIR ROSENZWEIG, STANISLAV SHWARTSMAN, RAANAN SADE, IGOR YANOVER, GAVRI BERGER, TOMER WEINER, RON GABOR
  • Restricting Clock Signal Delivery In A Processor
    Publication number: 20140380081
    Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, Larisa Novakovsky, George Leifman, Lev Makovsky, Ariel Sabba, Niv Tokman
  • Mapping A Performance Request To An Operating Frequency In A Processor
    Publication number: 20140380076
    Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Eliezer Weissmann, Efraim Rotem, Paul Diefenbaugh, Guy Therien, Nir Rosenzweig
  • Enabling A Non-Core Domain To Control Memory Bandwidth
    Publication number: 20140344598
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 20, 2014
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT
    Publication number: 20140325184
    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 30, 2014
    Inventors: Efraim Rotem, Eliezer Weissamann, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen
  • Metrology systems and methods
    Patent number: 8873054
    Abstract: Various metrology systems and methods are provided. One metrology system includes a light source configured to produce a diffraction-limited light beam, an apodizer configured to shape the light beam in the entrance pupil of illumination optics, and optical elements configured to direct the diffraction-limited light beam from the apodizer to an illumination spot on a grating target on a wafer and to collect scattered light from the grating target. The metrology system further includes a field stop and a detector configured to detect the scattered light that passes through the field stop. In addition, the metrology system includes a computer system configured to determine a characteristic of the grating target using output of the detector.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 28, 2014
    Assignee: KLA-Tencor Corp.
    Inventors: Daniel Kandel, Vladimir Levinski, Alexander Svizher, Joel Seligson, Andrew Hill, Ohad Bachar, Amnon Manassen, Yung-Ho Alex Chuang, Ilan Sela, Moshe Markowitz, Daria Negri, Efraim Rotem
  • Method and apparatus of power management of processor
    Patent number: 8874947
    Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: October 28, 2014
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Barnes Cooper, Guy Therien, Eliezer Weissmann, Anil Aggarwal
  • Method And Apparatus To Control Current Transients In A Processor
    Publication number: 20140317422
    Abstract: In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP controller may receive instruction width information associated with one or more instructions of an instruction queue prior to execution of the instructions by the execution unit. The IccP controller may determine an anticipated highest current level (Icc) for the at least one core based on the instruction width information. The IccP controller may generate a request for a first license for the at least one core that is associated with the Icc. Other embodiments are described and claimed.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 23, 2014
    Inventors: NIR ROSENZWEIG, ZEEV SPERBER, EFRAIM ROTEM
  • CONTROLLING POWER SUPPLY UNIT POWER CONSUMPTION DURING IDLE STATE
    Publication number: 20140281634
    Abstract: Methods and apparatus relating to controlling power consumption by a Power Supply Unit (PSU) during idle state are described. In one embodiment, a power supply unit enters a lower power consumption state (e.g. S9) based on power state information, corresponding to one or more components of the platform, and comparison of a first value (corresponding to a frequency/frequentness of entry into the lower power consumption state) to a first threshold value. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Inventors: EFRAIM ROTEM, BENJAMIN J. GOULD, JAMES G. HERMERDING, II, JORGE P. RODRIGUEZ, ALON NAVEH, NIR ROSENZWEIG, VIJAY S. R. DEGALAHAL
  • Enabling a non-core domain to control memory bandwidth in a processor
    Patent number: 8832478
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: September 9, 2014
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Wiessman, Ryan Wells
  • MULTI-LEVEL CPU HIGH CURRENT PROTECTION
    Publication number: 20140245034
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 30, 2011
    Publication date: August 28, 2014
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Dynamically allocating a power budget over multiple domains of a processor
    Patent number: 8775833
    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nadav Shulman
  • TOTAL PLATFORM POWER CONTROL
    Publication number: 20140189376
    Abstract: Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor and one or more components coupled to the processor are modified based on a total platform power consumption value. The platform, in turn, includes the processor and the one or more components. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Efraim Rotem, James G. Hermerding, II, Ruoying Ma, Jorge P. Rodriguez, Nir Rosenzweig
  • Dynamically allocating a power budget over multiple domains of a processor
    Patent number: 8769316
    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nadav Shulman
  • Power management coordination in multi-core processors
    Patent number: 8726048
    Abstract: Systems and methods of managing power provide for issuing a first operating requirement from a first processor core and issuing a second operating requirement from a second processor core. In one embodiment, the operating requirements can reflect either a power policy or a performance policy, depending upon the factor that is currently most important to software. Hardware coordination logic is used to coordinate a shared resource setting with the operating requirements. The hardware coordination logic is also able to coordinate the shared resource setting with independent resource settings of the first and second processor cores based on the operating requirements.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: May 13, 2014
    Assignee: Intel Corporation
    Inventors: Alon Naveh, Efraim Rotem, Eliezer Weissmann