Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor
    Publication number: 20130179704
    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: February 28, 2013
    Publication date: July 11, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nadav Shulman
  • Controlling A Turbo Mode Frequency Of A Processor
    Publication number: 20130179705
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2013
    Publication date: July 11, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Wiessmann, Ryan Wells, Nadav Shulman
  • Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor
    Publication number: 20130173941
    Abstract: In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.
    Type: Application
    Filed: February 28, 2013
    Publication date: July 4, 2013
    Inventors: Avinash N. Ananthakrishnan, Tomer Ziv, Doron Rajwan, Efraim Rotem
  • CONTROLLING POWER CONSUMPTION THROUGH MULTIPLE POWER LIMITS OVER MULTIPLE TIME INTERVALS
    Publication number: 20130173946
    Abstract: Methods and apparatus relating to controlling power consumption through multiple power limits over multiple time intervals are described. In one embodiment, the level of power consumption by a computing device component (e.g., a processor or one of its processor cores) is modified based on a determined power limit value. The power limit value may be determined based on rolling power consumption averages over multiple time intervals and their comparison against multiple corresponding power limits. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Inventors: Efraim Rotem, Avinash N. Ananthakrishnan, Doron Rajwan, Eliezer Weissmann, Alon Naveh, James G. Hermerding, II, Riad Durr, Hisham Abu Salah
  • COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT
    Publication number: 20130151569
    Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.
    Type: Application
    Filed: November 21, 2012
    Publication date: June 13, 2013
    Inventors: Guy Therien, Paul Diefenbaugh, Anil Aggarwal, Andrew Henroid, Jeremy Shrall, Efraim Rotem, Krishnakanth Sistla, Eliezer Weissmann, Mohan Kumar, Sarathy Jayakumar, Jose Andy Vargas, Neelam Chandwani, Michael A. Rothman, Robert Gough, Mark Doran
  • Method and apparatus of power management of processor
    Patent number: 8458498
    Abstract: A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: June 4, 2013
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Barnes Cooper, Guy Therien, Eliezer Weissmann, Anil Aggarwal
  • Metrology systems and methods
    Patent number: 8441639
    Abstract: Various metrology systems and methods are provided.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: May 14, 2013
    Assignee: KLA-Tencor Corp.
    Inventors: Daniel Kandel, Vladimir Levinski, Alexander Svizher, Joel Seligson, Andrew Hill, Ohad Bachar, Amnon Manassen, Yung-Ho Alex Chuang, Ilan Sela, Moshe Markowitz, Daria Negri, Efraim Rotem
  • Dynamically Controlling Cache Size To Maximize Energy Efficiency
    Publication number: 20130111121
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Wiessman, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Controlling Operating Frequency Of A Core Domain Via A Non-Core Domain Of A Multi-Domain Processor
    Publication number: 20130111236
    Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 2, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Jeremy J. Shrall, Eric C. Samson, Eliezer Wiessman, Ryan Wells
  • Controlling A Turbo Mode Frequency Of A Processor
    Publication number: 20130111226
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Wiessman, Ryan Wells, Nadav Shulman
  • Enabling A Non-Core Domain To Control Memory Bandwidth
    Publication number: 20130111120
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 2, 2013
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Wiessman, Ryan Wells
  • Estimating Temperature Of A Processor Core In A Low Power State
    Publication number: 20130080803
    Abstract: In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Itai Feit, Tomer Ziv, Doron Rajwan, Nadav Shulman, Alon Naveh
  • Controlling Temperature Of Multiple Domains Of A Multi-Domain Processor
    Publication number: 20130080804
    Abstract: In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Avinash N. Ananthakrishan, Tomer Ziv, Doron Rajwan, Efraim Rotem
  • Power management for multiple processor cores
    Patent number: 8402290
    Abstract: Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventors: Lev Finkelstein, Efraim Rotem, Aviad Cohen, Ronny Ronen, Doron Rajwan
  • Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor
    Publication number: 20130061064
    Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nadav Shulman
  • Determining An Effective Stress Level On A Processor
    Publication number: 20130054179
    Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Inventors: Dorit Shapira, Efraim Rotem, Douglas R. Moran
  • Power management for processing unit
    Patent number: 8386807
    Abstract: Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: February 26, 2013
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Dan Baum, Rajwan Doron, Omer Vikinski, Ronny Korner, Kosta Luria
  • Managing Power Consumption In A Multi-Core Processor
    Publication number: 20120254643
    Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.
    Type: Application
    Filed: March 16, 2012
    Publication date: October 4, 2012
    Inventors: Eric Fetzer, Reid J. Reidlinger, Don Soltis, William J. Bowhill, Satish Shrimali, Krishnakanth Sistla, Efraim Rotem, Rakesh Kumar, Vivek Garg, Alon Naveh, Lokesh Sharma
  • APPARATUS AND METHOD FOR HIGH CURRENT PROTECTION
    Publication number: 20120254641
    Abstract: An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Inventors: Efraim Rotem, Avinash N. Ananthakrishnan, Doron Rajwan, Kosta Luria, Ronny Korner
  • Method, Apparatus, and System for Energy Efficiency and Energy Conservation by Mitigating Performance Variations Between Integrated Circuit Devices
    Publication number: 20120221873
    Abstract: According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.
    Type: Application
    Filed: December 22, 2011
    Publication date: August 30, 2012
    Inventors: Ryan D. Wells, Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Gary A. Andrew