Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamically controlling cache size to maximize energy efficiency
    Patent number: 10564699
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Thread scheduling using processing engine information
    Patent number: 10545793
    Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov, Stephen H. Gunther, Monica Gupta, Efraim Rotem, Krishnakanth V. Sistla, Guy M. Therien, Ankush Varma, Eliezer Weissmann
  • System, Apparatus And Method For Loose Lock-Step Redundancy Power Management
    Publication number: 20200012329
    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
    Type: Application
    Filed: August 21, 2019
    Publication date: January 9, 2020
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Dynamically controlling cache size to maximize energy efficiency
    Patent number: 10474218
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT
    Publication number: 20190317773
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • System, apparatus and method for loose lock-step redundancy power management
    Patent number: 10429919
    Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Computing system and processor with fast power surge detection and instruction throttle down to provide for low cost power supply unit
    Patent number: 10429912
    Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistla, Martin Rowland, Efraim Rotem, Brian J. Griffith, Ankush Varma, Anupama Suryanarayanan
  • System power management
    Patent number: 10423202
    Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Tod F. Schiff, Doron Rajwan, Jeffrey M. Jull, James G. Hermerding, II, Nir Rosenzweig, Maytal Toledano, Alexander B. Uan-Zo-Li
  • Controlling a performance state of a processor using a combination of package and thread hint information
    Patent number: 10379904
    Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Israel Hirsh, Efraim Rotem, Doron Rajwan, Avinash N. Ananthakrishnan, Natanel Abitan, Ido Melamed, Guy M. Therien
  • Providing an interface for demotion control information in a processor
    Patent number: 10379596
    Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Nir Rosenzweig, Efraim Rotem, Yoav Ben-Raphael, Alon Naveh
  • User level control of power management policies
    Patent number: 10372197
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • Controlling performance states of processing engines of a processor
    Patent number: 10372198
    Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
  • Dynamically Controlling Cache Size To Maximize Energy Efficiency
    Publication number: 20190235611
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Processor Having Accelerated User Responsiveness In Constrained Environment
    Publication number: 20190235618
    Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
  • Enabling A Non-Core Domain To Control Memory Bandwidth
    Publication number: 20190212801
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 11, 2019
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • Forcing a processor into a low power state
    Patent number: 10345889
    Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
  • PROCESSOR, METHOD, AND SYSTEM FOR REDUCING LATENCY IN ACCESSING REMOTE REGISTERS
    Publication number: 20190205061
    Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Eliezer Weissmann, Alexander Gendler, Efraim Rotem, Moshe Cohen, Asit K. Mallick, Jason W. Brandt, Kameswar Subramaniam, Nathan Fellman, Hisham Shafi
  • System, Apparatus And Method For Controlling A Processor Based On Effective Stress Information
    Publication number: 20190204893
    Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Efraim Rotem, Esfir Natanzon, Doron Rajwan, Eliezer Weissmann, Dorit Shapira, Lily P. Looi, Bart Plackle, Nadav Shulman
  • System, Apparatus And Method For Processor-External Override Of Hardware Performance State Control Of A Processor
    Publication number: 20190196573
    Abstract: In one embodiment, a processor includes: one or more cores to execute instructions; a first request register to store hardware performance state control information for a first core of the one or more cores obtained from an operating system; a second request register to store hardware performance state control override information, the hardware performance state control override information to be received from a management controller coupled to the processor; and a power controller coupled to the one or more cores to control a performance state of the first core based at least in part on the hardware performance state override information when at least one override indicator of the second request register is set. Other embodiments are described and claimed.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Nikhil Gupta, Israel Hirsh, Esfir Natanzon, Nir Rosenzweig, Efraim Rotem, Guy M. Therien, Ankush Varma, Eliezer Weissmann
  • Controlling forced idle state operation in a processor
    Patent number: 10324519
    Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Yoni Aizik, Doron Rajwan, Gal Leibovich, Nadav Shulman, Hisham Abu Salah