Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
    Publication number: 20190155362
    Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 23, 2019
    Inventors: Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Avinash N. Ananthakrishnan, Dorit Shapira
  • MECHANISM FOR SAVING AND RETRIEVING MICRO-ARCHITECTURE CONTEXT
    Publication number: 20190155606
    Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventors: Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen
  • Apparatus and method for a user configurable reliability control loop
    Patent number: 10289514
    Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Eric Distefano, James G. Hermerding, II, Esfir Natanzon
  • Processor having accelerated user responsiveness in constrained environment
    Patent number: 10281975
    Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
  • Collaborative processor and system performance and power management
    Patent number: 10275260
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • Dynamically Controlling Cache Size To Maximize Energy Efficiency
    Publication number: 20190121422
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Dynamically Controlling Cache Size To Maximize Energy Efficiency
    Publication number: 20190121423
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Management of system current constraints with current limits for individual engines
    Patent number: 10268255
    Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Efraim Rotem, Alexander Gendler, Ankush Varma
  • THREAD SCHEDULING USING PROCESSING ENGINE INFORMATION
    Publication number: 20190102221
    Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov, Stephen H. Gunter, Monica Gupta, Efraim Rotem, Krishnakanth V. Sistla, Guy M. Therien, Ankush Varma, Eliezer Weissmann
  • Utilization Metrics for Processing Engines
    Publication number: 20190102274
    Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Hisham Abu Salah, Arthur Leonard Brown, Russell J. Fenger, Deepak Samuel Kirubakaran, Asit K. Mallick, Jacob Jun Pan, Srinivas Pandruvada, Efraim Rotem, Arjan Van De Ven, Eliezer Weissmann, Rafal J. Wysocki
  • THREAD SCHEDULING USING PROCESSING ENGINE INFORMATION
    Publication number: 20190102227
    Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Avinash Ananthakrishnan, Vijay Dhanraj, Russell Fenger, Vivek Garg, Eugene Gorbatov, Stephen Gunter, Monica Gupta, Efraim Rotem, Krishnakanth Sistla, Guy Therien, Ankush Verma, Eliezer Weissmann
  • Enabling a non-core domain to control memory bandwidth in a processor
    Patent number: 10248181
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • Processor voltage control using running average value
    Patent number: 10228755
    Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Efraim Rotem, Avinash N. Ananthakrishnan, Ankush Varma, Assaf Ganor, Nir Rosenzweig, David M. Pawlowski, Arik Gihon, Nadav Shulman
  • System maximum current protection
    Patent number: 10222851
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • Multi-level loops for computer processor control
    Patent number: 10216246
    Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Efraim Rotem, Eliezer Weissmann, Avinash N. Ananthakrishnan, Dorit Shapira
  • Efficient integrated switching voltage regulator comprising switches coupled to bridge drivers to provide regulated power supply to power domains
    Patent number: 10203742
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: February 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • OPERATING POINT MANAGEMENT IN MULTI-CORE ARCHITECTURES
    Publication number: 20190041966
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.
    Type: Application
    Filed: July 2, 2018
    Publication date: February 7, 2019
    Inventors: EFRAIM ROTEM, OREN LAMDAN, ALON NAVEH
  • System, Apparatus And Method For Responsive Autonomous Hardware Performance State Control Of A Processor
    Publication number: 20190041944
    Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.
    Type: Application
    Filed: June 20, 2018
    Publication date: February 7, 2019
    Inventors: Hisham Abu Salah, Efraim Rotem, Eliezer Weissmann, Yoni Aizik, Daniel D. Lederman
  • POWER MANAGEMENT BASED ON REAL TIME PLATFORM POWER SENSING
    Publication number: 20190041951
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.
    Type: Application
    Filed: June 19, 2018
    Publication date: February 7, 2019
    Inventors: Dorit Shapira, Anand K. Enamandram, Daniel Cartagena, Krishnakanth Sistla, Jorge P. Rodriguez, Efraim Rotem, Nir Rosenzweig
  • Mechanism for saving and retrieving micro-architecture context
    Patent number: 10191742
    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Boris Ginzburg, Alon Naveh, Nadav Shulman, Ronny Ronen