Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Forcing A Processor Into A Low Power State
    Publication number: 20180120924
    Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Application
    Filed: August 4, 2017
    Publication date: May 3, 2018
    Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
  • Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor
    Patent number: 9939879
    Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Jeremy J. Shrall, Eric C. Samson, Eliezer Weissmann, Ryan Wells
  • PROCESSOR VOLTAGE CONTROL USING RUNNING AVERAGE VALUE
    Publication number: 20180095520
    Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: DORON RAJWAN, EFRAIM ROTEM, AVINASH N. ANANTHAKRISHNAN, ANKUSH VARMA, ASSAF GANOR, NIR ROSENZWEIG, DAVID M. PAWLOWSKI, ARIK GIHON, NADAV SHULMAN
  • MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
    Publication number: 20180095932
    Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: DORON RAJWAN, EFRAIM ROTEM, ELIEZER WEISSMANN, AVINASH N. ANANTHAKRISHNAN, DORIT SHAPIRA
  • Controlling A Performance State Of A Processor Using A Combination Of Package And Thread Hint Information
    Publication number: 20180060123
    Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Eliezer Weissmann, Israel Hirsh, Efraim Rotem, Doron Rajwan, Avinash N. Ananthakrishnan, Natanel Abitan, Ido Melamed, Guy M. Therien
  • Providing lifetime statistical information for a processor
    Patent number: 9904339
    Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Dorit Shapira, Efraim Rotem, Doron Rajwan, Nadav Shulman, Esfir Natanzon, Nir Rosenzweig
  • Providing An Interface For Demotion Control Information In A Processor
    Publication number: 20180039322
    Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Eliezer Weissmann, Nir Rosenzweig, Efraim Rotem, Yoav Ben-Raphael, Alon Naveh
  • Management of System Current Constraints with Current Limits for Individual Engines
    Publication number: 20180004269
    Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Nir Rosenzweig, Efraim Rotem, Alexander Gendler, Ankush Varma
  • CONTROLLING PERFORMANCE STATES OF PROCESSING ENGINES OF A PROCESSOR
    Publication number: 20170371400
    Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 28, 2017
    Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
  • Controlling Forced Idle State Operation In A Processor
    Publication number: 20170371399
    Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Eliezer Weissmann, Efraim Rotem, Yoni Aizik, Doron Rajwan, Gal Leibovich, Nadav Shulman, Hisham Abu Salah
  • Processor Having Accelerated User Responsiveness In Constrained Environment
    Publication number: 20170371401
    Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Nir Rosenzweig, Eric Distefano, Ishmael F. Santos, James G. Hermerding, II
  • CURRENT CONTROL FOR A MULTICORE PROCESSOR
    Publication number: 20170364132
    Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 21, 2017
    Inventors: Alexander Gendler, Efraim Rotem, Nir Rosenzweig, Krishnakanth V. Sistla, Ashish V. Choubal, Ankush Varma
  • Computing system and processor with fast power surge detection and instruction throttle down to provide for low cost power supply unit
    Patent number: 9846463
    Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistla, Martin Mark Rowland, Efraim Rotem, Brian J. Griffith, Ankush Varma, Anupama Suryanarayanan
  • Method and apparatus for selecting an interconnect frequency in a computing system
    Patent number: 9811355
    Abstract: In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Efraim Rotem, Doron Rajwan, Nadav Shulman, Eliezer Weissmann
  • MULTI-LEVEL CPU HIGH CURRENT PROTECTION
    Publication number: 20170308146
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 8, 2017
    Publication date: October 26, 2017
    Applicant: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • SYSTEM POWER MANAGEMENT
    Publication number: 20170293332
    Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Applicant: Intel Corporation
    Inventors: EFRAIM ROTEM, TOD F. SCHIFF, DORON RAJWAN, JEFFREY M. JULL, JAMES G. HERMERDING, II, NIR ROSENZWEIG, MAYTAL TOLEDANO, ALEXANDER B. UAN-ZO-LI
  • Operating point management in multi-core architectures
    Patent number: 9785226
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Oren Lamdan, Alon Naveh
  • Controlling performance states of processing engines of a processor
    Patent number: 9760160
    Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
  • Forcing a processor into a low power state
    Patent number: 9760158
    Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
  • Method, apparatus, and system for energy efficiency and energy conservation by mitigating performance variations between integrated circuit devices
    Patent number: 9753516
    Abstract: According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Ryan D. Wells, Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Gary A. Andrew