Patents by Inventor Efraim Rotem

Efraim Rotem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Providing an asymmetric multicore processor system transparently to an operating system
    Patent number: 9720730
    Abstract: In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Boris Ginzburg, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli, Alon Naveh, David A. Koufaty, Scott D. Hahn, Tong Li, Avi Mendleson, Eugene Gorbatov, Hisham Abu-Salah, Dheeraj R. Subbareddy, Paolo Narvaez, Aamer Jaleel, Efraim Rotem, Yuval Yosef, Anil Aggarwal, Kenzo Van Craeynest
  • Controlling a guaranteed frequency of a processor
    Patent number: 9710043
    Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 18, 2017
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Weissmann, Hisham Abu Salah, Efraim Rotem, Guy M. Therien, Nadav Shulman, Esfir Natanzon, Paul S. Diefenbaugh
  • Method and apparatus for determining thread execution parallelism
    Patent number: 9684541
    Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Arik Gihon, Efraim Rotem, Paul S. Diefenbaugh, Eric C. Samson, Michael Mishaeli, Yoni Aizik, Chen Ranel
  • POWER CONSUMPTION MONITORING DEVICE FOR A POWER SOURCE
    Publication number: 20170168118
    Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 15, 2017
    Applicant: INTEL CORPORATION
    Inventors: Efraim Rotem, NIR ROSENZWEIG, JEFFREY A. CARLSON, PHILIP R. LEHWALDER, NADAV SHULMAN, Doron Rajwan
  • Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency
    Patent number: 9671853
    Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Yoni Aizik, Eliezer Weissmann, Efraim Rotem, Yevgeni Sabin, Doron Rajwan, Ahmad Yasin
  • ENHANCING POWER-PERFORMANCE EFFICIENCY IN A COMPUTER SYSTEM WHEN BURSTS OF ACTIVITY OCCURS WHEN OPERATING IN LOW POWER
    Publication number: 20170147054
    Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.
    Type: Application
    Filed: February 7, 2017
    Publication date: May 25, 2017
    Inventors: HISHAM ABU SALAH, ELIEZER WEISSMANN, EFRAIM ROTEM, PAUL S. DIEFENBAUGH, JAY D. SCHWARTZ, SHARAD C. TRIPATHI
  • Adjusting power consumption of a processing element based on types of workloads to be executed
    Patent number: 9652018
    Abstract: Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
  • Dynamically Optimizing Power Management Operational Parameters Of A Processor
    Publication number: 20170131754
    Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Shmuel Zobel, Maxim Levit, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Dorit Shapira, Nadav Shulman
  • Controlling a turbo mode frequency of a processor
    Patent number: 9618997
    Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells, Nadav Shulman
  • Operating point management in multi-core architectures
    Patent number: 9619009
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at a performance level different than a performance level at which another one of the plurality of processor cores may operate. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Oren Lamdan, Alon Naveh
  • Enabling A Non-Core Domain To Control Memory Bandwidth
    Publication number: 20170097668
    Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
    Type: Application
    Filed: December 16, 2016
    Publication date: April 6, 2017
    Inventors: Avinash N. Ananthakrishnan, Inder M. Sodhi, Efraim Rotem, Doron Rajwan, Eliezer Weissmann, Ryan Wells
  • Controlling power consumption by power management link
    Patent number: 9612652
    Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Efraim Rotem, Jawad Haj-Yihia, Ohad Falik
  • User Level Control Of Power Management Policies
    Publication number: 20170083076
    Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Inventors: Krishnakanth V. Sistla, Jeremy Shrall, Stephen H. Gunther, Efraim Rotem, Alon Naveh, Eliezer Weissmann, Anil Aggarwal, Martin T. Rowland, Ankush Varma, Ian M. Steiner, Matthew Bace, Avinash N. Ananthakrishnan, Jason Brandt
  • INTEGRATING A POWER ARBITER IN A PROCESSOR
    Publication number: 20170083067
    Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Assaf Ganor, Efraim Rotem, Noam Winer, Omer Vikinski
  • Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power
    Patent number: 9600058
    Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Hisham Abu Salah, Eliezer Weissmann, Efraim Rotem, Paul S. Diefenbaugh, Jay D. Schwartz, Sharad C. Tripathi
  • SYSTEM MAXIMUM CURRENT PROTECTION
    Publication number: 20170038815
    Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Nadav Shulman, Gal Leibovich, Tomer Ziv, Amit Gabai, Jorge P. Rodriguez, Jeffrey A. Carlson
  • EFFICIENT INTEGRATED SWITCHING VOLTAGE REGULATION
    Publication number: 20170031419
    Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: Gregory Sizikov, Michael Zelikson, Efraim Rotem, Eyal Fayneh
  • Extension of CPU Context-State Management for Micro-Architecture State
    Publication number: 20170024210
    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.
    Type: Application
    Filed: June 7, 2016
    Publication date: January 26, 2017
    Inventors: Efraim Rotem, Eliezer Weissmann, Michael Mishaeli, Boris Ginzburg, Alon Naveh
  • Dynamically Controlling Cache Size To Maximize Energy Efficiency
    Publication number: 20170010656
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT
    Publication number: 20170003724
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: September 12, 2016
    Publication date: January 5, 2017
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann