Patents by Inventor Eiichi Nishimura
Eiichi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8357615Abstract: The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric conType: GrantFiled: June 30, 2008Date of Patent: January 22, 2013Assignee: Tokyo Electron LimitedInventors: Yuki Chiba, Eiichi Nishimura, Ryuichi Asako
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Patent number: 8353986Abstract: In a substrate processing apparatus comprising a processing unit where a specific type of processing is executed on a wafer and a transfer chamber through which a wafer is carried into/out of the processing unit, the transfer chamber includes an air intake unit through which external air is drawn into the transfer chamber, a discharge unit disposed so as to face opposite the air intake unit, through which the discharge gas in the transfer chamber is discharged and a discharge gas filtering means disposed at the discharge unit and constituted with a harmful constituent eliminating filter through which a harmful constituent contained in the discharge gas, at least, is eliminated.Type: GrantFiled: March 29, 2006Date of Patent: January 15, 2013Assignee: Tokyo Electron LimitedInventors: Yoshiaki Sasaski, Yusuke Muraki, Eiichi Nishimura, Yuko Ono
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Patent number: 8329050Abstract: A substrate processing method for processing a substrate, on which a processing target layer, an intermediate layer, and a mask layer having an opening to expose a part of the intermediate layer are stacked in this order, includes a shrink etching step. In the shrink etching step, an opening width of the opening of the mask layer is reduced by depositing deposits on a sidewall surface thereof by a plasma generated from a gaseous mixture of depositive gas expressed by a general formula CxHyFz (x, y and z being positive integers) and SF6 gas. Also, there is formed in the intermediate layer an opening having an opening width corresponding to the reduced opening width of the opening of the mask layer by etching the intermediate layer.Type: GrantFiled: August 21, 2009Date of Patent: December 11, 2012Assignee: Tokyo Electron LimitedInventors: Takashi Sone, Eiichi Nishimura
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Publication number: 20120270406Abstract: A plasma processing apparatus in which a cleaning method is performed includes a plasma generating chamber, having a silicon-containing member, for generating therein plasma by exciting a processing gas; a plasma processing chamber communicating with the plasma generating chamber via a partition member; and a high frequency antenna, having a planar shape, provided at an outside of a dielectric window of the plasma generating chamber. The cleaning method includes exciting a hydrogen-containing processing gas into plasma in the plasma generating chamber, introducing hydrogen radicals in the plasma into the plasma processing chamber through the partition member, performing a plasma process on a processing target substrate by allowing the hydrogen radicals to act on the processing target substrate, unloading the processing target substrate, and removing silicon-based deposits generated in the plasma generating chamber by introducing a tetrafluoride (tetrafluoromethane) gas into the plasma generating chamber.Type: ApplicationFiled: April 13, 2012Publication date: October 25, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Shigeru Tahara, Eiichi Nishimura
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Publication number: 20120244716Abstract: There is provided a substrate processing method capable of etching a layer containing, at least, platinum without using a halogen gas. When etching the platinum-manganese layer on a wafer W by using a tantalum (Ta) layer 38 having a certain pattern shape, a processing gas containing, at least, a carbon monoxide gas, a hydrogen gas, and a rare gas is used, and a ratio of a gas flow rate of the hydrogen gas to a total gas flow rate of the carbon monoxide gas and the hydrogen gas is in a range of from about 50% to about 75%.Type: ApplicationFiled: March 21, 2012Publication date: September 27, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Takashi Sone, Eiichi Nishimura
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Publication number: 20120244718Abstract: Disclosed is a substrate processing method capable of preventing an etching rate from being deteriorated when a high aspect ratio hole or trench is formed on an oxide film. When a high aspect ratio hole or trench is formed on an oxide film by etching the oxide film formed on a wafer using a hard mask layer having an opening and made of silicon, the oxide film corresponding to the opening is etched using plasma generated from a processing gas containing a C4F6 gas and a methane gas. Subsequently, a reactive product generated by the etching and deposited on an inner surface of the hole of the oxide film is ashed with plasma generated from a processing gas containing an oxygen gas, and the etching and the ashing processes are repeated in sequence.Type: ApplicationFiled: March 23, 2012Publication date: September 27, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi NISHIMURA, Masato KUSHIBIKI, Fumiko YAMASHITA
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Patent number: 8273258Abstract: A disclosed fine pattern forming method includes steps of: forming patterns made of a first photoresist film, arranged at a first pitch on a film; trimming the patterns made of the first photoresist film; depositing a protection film on the patterns made of the first photoresist film on the trimmed patterns made of the first photoresist film, the protection film being made of reaction products of an etching gas, thereby obtaining first patterns; forming other patterns made of a second photoresist film, arranged at a second pitch, on the protection film, the other patterns made of the second photoresist film being shifted by half of the first pitch from the corresponding patterns made of the first photoresist film; trimming the other patterns made of the second photoresist film into second patterns; and etching the film using the first patterns and the second patterns.Type: GrantFiled: January 4, 2010Date of Patent: September 25, 2012Assignee: Tokyo Electron LimitedInventors: Takashi Sone, Eiichi Nishimura
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Patent number: 8262921Abstract: An ashing process in which an etching mask is removed through ashing by supplying hydrogen radicals toward a wafer W being heated to a predetermined temperature and a restoration process in which the film quality of a low dielectric constant insulating film having been damaged during an etching process is restored while, at the same time, rendering the low dielectric constant insulating film exposed at a recessed portion into a hydrophobic state by supplying a gas containing a ?-diketone compound with an ignition point equal to or higher than 300° C. toward the wafer W having undergone the ashing process, are executed.Type: GrantFiled: November 24, 2008Date of Patent: September 11, 2012Assignee: Tokyo Electron LimitedInventor: Eiichi Nishimura
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Patent number: 8252698Abstract: In a substrate processing method of processing a substrate in which a processing target layer, an intermediate layer, and a mask layer are stacked one on top of another, the mask layer having an opening that partially exposes the intermediate layer, a thickness of the mask layer is increased by depositing deposits on an upper surface of the mask layer with plasma generated from a mixed gas of SF6 gas and a depositive gas represented in a general equation, CxHyFz (where, x, y, and z are positive integers).Type: GrantFiled: September 11, 2009Date of Patent: August 28, 2012Assignee: Tokyo Electron LimitedInventors: Masato Kushibiki, Eiichi Nishimura
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Publication number: 20120214315Abstract: In a substrate processing method, a polysilicon layer 38 on a wafer W is etched with a bromine cation 45a and a bromine radical 45b in plasma generated from a processing gas containing a hydrogen bromide gas, an oxygen gas, and a nitrogen trifluoride gas, and then, is ashed with an oxygen radical 46 and a nitrogen radical 47 in plasma generated from a processing gas containing an oxygen gas and a nitrogen gas. Thereafter, the polysilicon layer 38 is etched with a fluorine cation 48a and a fluorine radical 48b in plasma generated from a processing gas containing an argon gas and a nitrogen trifluoride gas. While the polysilicon layer 38 is ashed, an oxidation process is performed on a silicon bromide generated by etching the polysilicon layer 38 with the bromine cation 45a.Type: ApplicationFiled: February 20, 2012Publication date: August 23, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi Nishimura, Takashi Sone, Fumiko Yamashita
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Patent number: 8241511Abstract: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.Type: GrantFiled: October 9, 2008Date of Patent: August 14, 2012Assignee: Tokyo Electron LimitedInventors: Masato Kushibiki, Eiichi Nishimura
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Publication number: 20120196387Abstract: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.Type: ApplicationFiled: March 8, 2012Publication date: August 2, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Masato KUSHIBIKI, Eiichi NISHIMURA
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Publication number: 20120190207Abstract: A plasma processing apparatus performs plasma process by using a hydrogen radical generated by plasma-exciting a process gas containing hydrogen on a substrate to be processed. A high-frequency antenna includes an antenna device that is configured to resonate at a half-wavelength of high-frequency power applied from the high-frequency power source by opening two ends of the antenna device and grounding a center point of the antenna device. A barrier wall member for separating a plasma generating chamber and a plasma processing chamber includes a plurality of plate-shaped members having a plurality of openings through which the hydrogen radical passes, formed of an insulating material through which UV light does not pass, and overlapping each other at a predetermined interval, wherein the openings of one plate-shaped member are provided not to overlap the openings of another plate-shaped member.Type: ApplicationFiled: January 24, 2012Publication date: July 26, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi NISHIMURA, Shigeru TAHARA
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Publication number: 20120190206Abstract: A semiconductor device manufacturing method includes forming a first organic film pattern on a to-be-etched layer on a substrate, forming a silicon oxide film coating the first organic film pattern-etching the silicon oxide film to form a first mask pattern to cause the width of the line part of the first organic film pattern to have a fixed proportion with respect forming a second organic film pattern coating the silicon oxide film, forming a second mask pattern including the silicon oxide film on a side face part in an area coated by the second organic film pattern, and forming, in an area other than the area coated by the second organic film pattern, a third mask pattern in which an even number of the silicon oxide films are arranged.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: Tokyo Electron LimitedInventors: Koichi YATSUDA, Eiichi NISHIMURA
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Publication number: 20120180475Abstract: An actuator 10 includes a main body 14 having a displacement unit 11 and electrodes 12 and 13 configured to apply a voltage to the displacement unit 11, the displacement unit being made of a mixture of a silicone-containing elastomer and an ionic liquid, and being displaced by applying a voltage between the electrodes; and a displacement transmission unit 15 configured to be displaced in an out-of-plane direction by displacement of the displacement unit 11.Type: ApplicationFiled: September 28, 2010Publication date: July 19, 2012Applicants: UNIVERSITY OF YAMANASHI, TOKYO ELECTRON LIMITEDInventors: Masahiro Shimizu, Shigekazu Komatsu, Eiichi Nishimura, Yoshio Kimura, Takahiko Ooasa, Hidenori Okuzaki
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Patent number: 8210742Abstract: A foreign matter detecting method of detecting foreign matter attached to a peripheral edge of a substrate, which makes it possible to accurately detect foreign matter attached to the peripheral edge of the substrate even if the foreign matter is of a minute size below the detection limit of an existing measuring instrument, and which is highly versatile and suitable for mass production of substrates. The substrate is cooled to condense moisture around the foreign matter attached to the peripheral edge of the substrate, and then the condensed moisture is iced to grow an ice crystal. Then, the foreign matter attached to the peripheral edge of the substrate, which is emphasized by the ice crystal, is detected.Type: GrantFiled: July 21, 2009Date of Patent: July 3, 2012Assignee: Tokyo Electron LimitedInventors: Tsuyoshi Moriya, Eiichi Nishimura
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Publication number: 20120164839Abstract: There is provided a substrate processing method capable of increasing an etching rate of a copper member without using a halogen gas. A Cu layer 40 having a smoothened surface 50 is obtained, and then, a processing gas produced by adding a methane gas to a hydrogen gas is introduced into an inner space of a processing chamber 15. Plasma is generated from this processing gas. In the inner space of the processing chamber 15, there exist oxygen radicals 52 generated when an oxide layer 42 is etched, and carbon radicals 53 generated from methane. The oxygen radicals 52 and the carbon radicals 53 are compounded to generate an organic acid, and the organic acid makes a reaction with copper atoms of the Cu layer 40. As a result, a complex of the organic acid having the copper atoms is generated, and the generated organic acid complex is vaporized.Type: ApplicationFiled: December 21, 2011Publication date: June 28, 2012Applicant: TOKYO ELECTRON LIMITEDInventor: Eiichi Nishimura
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Patent number: 8202805Abstract: A method for processing a substrate including a processing target layer and an organic film, include: a deposition/trimming process of forming a reinforcement film on a surface of the organic film and, at the same time, trimming a line width of a line portion of the organic film constituting an opening pattern. The deposition/trimming process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto the surface of the organic film and an oxidation process in which the line width of the organic film is trimmed while the adsorbed silicon-containing gas is converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.Type: GrantFiled: March 9, 2010Date of Patent: June 19, 2012Assignee: Tokyo Electron LimitedInventors: Masato Kushibiki, Eiichi Nishimura
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Patent number: 8198183Abstract: A feedforward control is performed so that a line width of a mask constituted by an Si3N4 layer 102 formed by using a photoresist 105b as a mask is to be the same as a line width of a mask pattern constituted by an SiO2 layer 103 based on a measured line width of the photoresist 105b and the measured line width of the mask pattern constituted by the SiO2 layer 103. For example, a control of a trimming amount of the line width of the photoresist 105b is performed so that the line width of the photoresist 105b is to be the same as the line width of the mask pattern constituted by the SiO2 layer 103.Type: GrantFiled: October 23, 2008Date of Patent: June 12, 2012Assignee: Tokyo Electron LimitedInventors: Koichi Yatsuda, Eiichi Nishimura
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Patent number: 8173357Abstract: The method of forming an etching mask includes: forming a mask layer on an object layer that is to be etched, to form an etching mask used in etching the object layer; forming a first mask layer on the mask layer, the first mask layer having a first pattern that is to be transferred onto the mask layer; forming a second mask layer on the first mask layer, the second mask layer having a second pattern that is to be transferred onto the mask layer; obtaining a third mask layer having the first pattern and the second pattern, by transferring the second pattern of the second mask layer onto the first mask layer; and forming the etching mask used in the etching of the object layer, by etching the mask layer using the third mask layer.Type: GrantFiled: March 19, 2009Date of Patent: May 8, 2012Assignee: Tokyo Electron LimitedInventor: Eiichi Nishimura