Abstract: A controller and a control method for a controller can simplify application development and can improve the performance of device control processes. When a request is received from an application 1 and the received process request is an initialization request, whether or not the received request is the first initialization request received after the application 1 started running is determined. If the received initialization request is the first initialization request, the request is passed to the device driver 3 and initialization settings information describing the configuration of the device driver 3 after the initialization process ends is stored. If an error has occurred in the device driver 3 when the device driver 3 status is detected, an error handling process is executed according to the device driver 3 state. When the device driver 3 has recovered, a request for setting the device driver 3 state to the state based on the initialization settings information is asserted.

Abstract: A media processing device enables continuous high-speed processing of recording media. A media processing device has a magnetic head 21 that reads information recorded on checks 4 in the check 4 conveyance path 10, a magnetic recognition unit 20b that acquires the result of a verification based on information read by the magnetic head 21, and a conveyance control unit 20a that starts conveying the check 4 to be processed next. The conveyance control unit 20a selectively operates in an individual processing mode that starts conveying the check 4 to be read next after the results of verifying the read data are acquired by the magnetic recognition unit 20b, and a continuous processing mode that starts conveying the check 4 to be read next after the magnetic head 21 reads at least part of the information without waiting for the magnetic head 21 to acquire the complete verification result.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.

Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

Abstract: A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.

Abstract: Manufacturing a nonvolatile storage device including: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a substrate; processing the first electrode film and the first storage unit film into a strip shape; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the sacrifice layer; forming a mask layer on the second electrode film; processing the second electrode film into a strip shape using the mask layer; removing a portion of the first storage unit film exposed from the sacrifice layer using the mask layer processing the first storage unit film into a columnar shape, removing the sacrifice layer exposing the first storage unit film; and removing the exposed first storage unit film.

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.

Abstract: A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

Abstract: A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Abstract: A controller and a control method for a controller can simplify application development and can improve the performance of device control processes. When a request is received from an application 1 and the received process request is an initialization request, whether or not the received request is the first initialization request received after the application 1 started running is determined. If the received initialization request is the first initialization request, the request is passed to the device driver 3 and initialization settings information describing the configuration of the device driver 3 after the initialization process ends is stored. If an error has occurred in the device driver 3 when the device driver 3 status is detected, an error handling process is executed according to the device driver 3 state. When the device driver 3 has recovered, a request for setting the device driver 3 state to the state based on the initialization settings information is asserted.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.

Abstract: A method for manufacturing a nonvolatile storage device including: a plurality of first electrodes aligning in a first direction; a plurality of second electrodes aligning in a second direction nonparallel to the first direction and provided above the first electrodes; and a first storage unit provided between the first electrode and the second electrode and including a first storage layer, a resistance of the first storage layer changing by at least one of an applied electric field and an applied current, the method includes: stacking a first electrode film forming a first electrode and a first storage unit film forming a first storage unit on a major surface of a substrate; processing the first electrode film and the first storage unit film into a strip shape aligning in the first direction; burying a sacrifice layer between the processed first electrode films and between the processed first storage unit films; forming a second electrode film forming a second electrode on the first storage unit film and the

Abstract: A plastic lens, which does not require a modification to an inner diameter of a mirror frame but is uniform in outer diameter, is provided and include: protrusions on the circumference in at least three points divided thereof into three equal parts except for an injection gate point, in positions equally distant to a center O of the plastic lens. The protrusions have respective outer surfaces provided as fit portions to a mirror frame. The plastic lens preferably has a diameter of 50 mm or more and a thickness smallest at the center thereof.

Abstract: An assembling method for an assembly is provided: the assembly comprising a cell structure (1) housed and held in a metal vessel (5) via a compressible material having a cushioning property (7) by arranging it between outer periphery of the structure (1) and the vessel (5) in a compressed state with applying a mounting pressure to the structure (1) via the material (7) to hold the structure (1) in the vessel (5). Information regarding outside dimension of the structure (1) and/or inside dimension of the vessel (5) being marked on their surfaces prior to the start of assembly, and the information is read, and a cell structure (1) and a metal vessel (5) are selected based on read information in assembly to achieve a proper holding condition therebetween. Regardless of variations in external dimension of the structure, etc. constituting the assembly, the minimization thereof, and proper holding state may be achieved easily without causing a fracture of the structure, etc.

Abstract: A semiconductor device comprising a plurality of first wirings provided in a predetermined layer on a substrate with being lined up, and formed to extend longer or contract shorter from one side toward the other side along a direction in which the first wirings are lined up, adjacent one-end portions of the first wirings being arranged in positions displaced from one another in a direction crossing at right angles the direction in which the first wirings are lined up.

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.