Patents by Inventor Eran Sharon
Eran Sharon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118736Abstract: Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Exemplary processing engines include a Read engine, a Write engine, etc. A recursive least-squares update procedure is also described.Type: ApplicationFiled: October 3, 2022Publication date: April 11, 2024Inventors: Yoseph Hassan, Eran Sharon, Shay Benisty, Ariel Navon
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Publication number: 20240111438Abstract: Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to measure a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Procedures are also provided for assessing the accuracy of the power-per-processing event values and for controlling further operations based on the assessment.Type: ApplicationFiled: April 7, 2023Publication date: April 4, 2024Inventors: Ariel Navon, Eran Sharon, Yoseph Hassan, Shay Benisty
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Patent number: 11914862Abstract: An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.Type: GrantFiled: March 22, 2022Date of Patent: February 27, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, Idan Alrod, Eran Sharon
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Patent number: 11868646Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a read threshold on a wordline, adjust a read threshold voltage level associated with the read threshold, determine an adjusted read threshold at the adjusted read threshold voltage level, where the adjusted read threshold is different from the read threshold, compare the adjusted read threshold to the read threshold, and calibrate the read threshold based on the comparing. The controller is further configured to analyze a bit error rate (BER) difference based on the calibrating and/or a previous read threshold voltage level movement, choose a next target read threshold for next calibration, and read a second page at the next target read threshold.Type: GrantFiled: November 1, 2021Date of Patent: January 9, 2024Assignee: Western Digital Technologies, Inc.Inventors: Tomer Eliash, Alexander Bazarsky, Eran Sharon
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Patent number: 11860733Abstract: Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.Type: GrantFiled: December 8, 2021Date of Patent: January 2, 2024Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Ran Zamir, David Avraham, Idan Alrod
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Publication number: 20230420059Abstract: Before a read threshold is needed to read a wordline in memory, a data storage device can infer a plurality of read thresholds based on possible conditions of the memory that may exist when the read threshold is eventually needed. When the read threshold is needed, it is selected from the previously-inferred read thresholds based on the current conditions of the memory. This can improve latency and throughput, improve quality of service, reduce power consumption, and reduce errors.Type: ApplicationFiled: September 5, 2023Publication date: December 28, 2023Applicant: Western Digital Technologies, Inc.Inventors: David Avraham, Alexander Bazarsky, Eran Sharon, Ariel Navon
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Storage System and Method for Implementation of Symmetric Tree Models for Read Threshold Calibration
Publication number: 20230410869Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.Type: ApplicationFiled: August 30, 2022Publication date: December 21, 2023Applicant: Western Digital Technologies, Inc.Inventors: Eran Sharon, Ariel Navon, Alexander Bazarsky, David Avraham, Nika Yanuka, Idan Alrod -
Storage System and Method for Inference of Read Thresholds Based on Memory Parameters and Conditions
Publication number: 20230402112Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Applicant: Western Digital Technologies, Inc.Inventors: Eran Sharon, Ariel Navon, Alexander Bazarsky, David Avraham, Nika Yanuka, Idan Alrod, Tsiko Shohat Rozenfeld, Ran Zamir -
Publication number: 20230402072Abstract: A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.Type: ApplicationFiled: July 11, 2023Publication date: December 14, 2023Applicant: Western Digital Technologies, Inc.Inventors: Alexander Bazarsky, Ariel Navon, Eran Sharon, David Avraham, Nika Yanuka, Idan Alrod
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Publication number: 20230376227Abstract: The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data “temperature” (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.Type: ApplicationFiled: May 23, 2022Publication date: November 23, 2023Applicant: Western Digital Technologies, Inc.Inventors: Ariel NAVON, Idan ALROD, David AVRAHAM, Eran SHARON, Vered KELNER
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Patent number: 11822820Abstract: A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.Type: GrantFiled: November 10, 2021Date of Patent: November 21, 2023Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, Eran Sharon, Idan Alrod
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Publication number: 20230326528Abstract: A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be based on a temperature change or a bit error rate (BER). The read level tracking method includes determining the BER of an indicative word line, determining an adjusted read threshold level based on the BER, and adjusting read threshold levels according to the adjusted read threshold level.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Applicant: Western Digital Technologies, Inc.Inventors: Eran Sharon, Nika Yanuka, Idan Alrod, Alexander Bazarsky, Evgeny Mekhanik
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Publication number: 20230305703Abstract: An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Applicant: Western Digital Technologies, Inc.Inventors: Ran Zamir, Idan Alrod, Eran Sharon
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Patent number: 11763911Abstract: A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data.Type: GrantFiled: October 5, 2021Date of Patent: September 19, 2023Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Idan Alrod
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Patent number: 11762735Abstract: Interleaved ECC coding for key-value data storage devices. In one embodiment, a controller includes a memory interface including a namespace database; an ECC engine; a controller memory; and an electronic processor. The electronic processor is configured to receive a host write command, determine whether write access was setup as a key-value (KV) namespace in the namespace database and is associated with the host write command, and control the ECC engine and the memory interface to perform one or more program operations on the data in the memory using the interleaved ECC coding and based on the host write command in response to determining that the write access was setup as the KV namespace in the namespace database and the KV namespace is associated with the host write command.Type: GrantFiled: October 1, 2021Date of Patent: September 19, 2023Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, David Avraham, Alexander Bazarsky, Eran Sharon
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Patent number: 11755407Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.Type: GrantFiled: May 26, 2021Date of Patent: September 12, 2023Assignee: Western Digital Technologies, Inc.Inventors: Dudy David Avraham, Ran Zamir, Eran Sharon
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Patent number: 11727984Abstract: Data storage devices, such as solid state drives (SSDs), are disclosed. A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.Type: GrantFiled: February 24, 2021Date of Patent: August 15, 2023Assignee: Western Digital Technologies, Inc.Inventors: Eran Sharon, Karin Inbar, Alexander Bazarsky, Dudy David Avraham, Rohit Sehgal, Gilad Koren
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Patent number: 11694721Abstract: A data storage device includes a hard disk drive coupled to a printed circuit board (PCB), a volatile memory device coupled to the PCB, a non-volatile memory device coupled to the PCB, and a controller coupled to the PCB, such that the controller is in communication with the hard disk drive, the volatile memory device, and the non-volatile memory device. The controller is configured to identify patterns and/or structures of metadata for the hard disk drive, perform one or more of the following to the metadata to tailor the metadata: data shaping, content aware decoding, adaptive data trimming, and/or adaptive metablock sizing, and write the tailored metadata to the non-volatile memory device. The metadata is at least one of repeatable run out metadata, positioning error signal metadata, adjacent track interference metadata, and/or emergency power off metadata.Type: GrantFiled: September 30, 2021Date of Patent: July 4, 2023Assignee: Western Digital Technologies, Inc.Inventors: Gilat Flaishman, Stella Achtenberg, Omer Fainzilber, Eran Sharon, David Robison Hall
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Patent number: 11681581Abstract: Effective use of cyclic redundancy check (CRC) signatures is achieved where each sector of a flash management unit (FMU) has a distinct CRC signature. The CRC signatures are XORed together to create a total CRC signature for the FMU. When a host device updates a single sector of the FMU, the CRC signature for the updated single sector can be changed by removing the old CRC signature corresponding to the single sector and replacing the old CRC signature with a new CRC signature corresponding to the updated single sector. The old CRC signature is XORed from the total CRC signature and then the new CRC signature is XORed with the remaining CRC signatures to create a new total CRC signature. In so doing, data integrity is ensured.Type: GrantFiled: June 21, 2022Date of Patent: June 20, 2023Assignee: Western Digital Technologies, Inc.Inventors: Ishai Ilani, Ran Zamir, Karin Inbar, Eran Sharon, Idan Alrod
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Patent number: 11675534Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.Type: GrantFiled: October 20, 2022Date of Patent: June 13, 2023Assignee: Western Digital Technologies, Inc.Inventors: Julian Vlaiko, Idan Alrod, Tien-Chien Kuo, Nimrod Hermesh, Eran Sharon