Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.

Abstract: Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.

Abstract: A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.

Abstract: A memory controller including, in one implementation, a memory interface and a control circuit. The memory interface is configured to receive a punctured codeword read from a non-volatile memory. The control circuit is configured to determine error probability values for a plurality of check nodes associated with a punctured bit included in the punctured codeword. The control circuit is also configured to determine an error probability value for the punctured bit based on the error probability values for the plurality of check nodes associated with the punctured bit and a variable degree associated with the punctured bit. The control circuit is further configured to determine a log likelihood ratio (LLR) value for the punctured bit based on the error probability value for the punctured bit. The control circuit is also configured to decode the punctured codeword using the LLR value for the punctured bit.

Abstract: A memory includes, in one embodiment, NAND elements; read/write circuitry; and compressed soft-bit circuitry. The compressed soft-bit circuitry is configured to determine or receive one or more NAND conditions and then determine a soft-bit delta and select a compression scheme based on the NAND conditions. The read/write circuitry is configured to read a set of hard bits from the NAND elements and sense a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the NAND elements. The first set of soft-bits has a first fixed size, and each soft-bit of the first set of soft-bits indicates a reliability of a corresponding hard bit of the set of hard bits. The compressed soft-bit circuitry is also configured to generate a second set of soft-bits based on the selected compression scheme and output the second set of soft-bits to a controller.

Abstract: A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

Abstract: A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.

Abstract: Read reference levels are calibrated by calibrating integration times. An integration time is the length of time for which the charge on a sense node is allowed to change while the memory cell is being sensed. Calibrating the integration time is much faster than calibrating the reference voltage itself. This is due, in part, to reducing the number of different reference voltages that need to be applied during calibration. Calibrating the integration time may use different test integration times for a given read reference voltage, thereby reducing the number of read reference voltages. Hence, calibrating the integration time(s) is very efficient timewise. Also, power consumption may be reduced.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. During a boot operation, the controller is configured to determine whether the boot is a device boot or a host boot. The controller includes a boot optimization unit. The boot optimization unit or the controller is configured to collect statistics of the fetched data, predict the data to be fetched next, and speculatively fetch the data. The controller further includes a rearrangement unit. The controller or the rearrangement unit is configured to rearrange data in the memory device based on the collect statistics of the fetched data so that the next boot operation is more optimized than the current boot operation.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. During a boot operation, the controller is configured to determine whether the boot is a device boot or a host boot. The controller includes a boot optimization unit. The boot optimization unit or the controller is configured to collect statistics of the fetched data, predict the data to be fetched next, and speculatively fetch the data. The controller further includes a rearrangement unit. The controller or the rearrangement unit is configured to rearrange data in the memory device based on the collect statistics of the fetched data so that the next boot operation is more optimized than the current boot operation.

Abstract: A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. To improve the accuracy of recovering the encoded foggy phase data, techniques are presented to calibrate the voltage levels used in sensing the foggy state distributions.

Abstract: A control circuit on a control die compensates for interference caused by adjacent memory cells on target memory cells on a memory die. The compensation may be based on the data states of the adjacent memory cells. Data latches may be used to store data states of the memory cells. However, reading the target memory cells can over-write the data states of the adjacent memory cells in the data latches. The control die may store data state information for the adjacent memory cells prior to sensing the target memory cells (e.g., prior to a decoding error of a codeword in the target cells). Saving the data state information on the control die reduces storage requirements of the memory die and alleviates the need to sense the adjacent memory cells again if decoding the codeword in the target memory cells fails.

Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Abstract: An apparatus includes memory arrays and a power-performance-endurance manager module. The power-performance-endurance manager module stores a power-endurance state descriptor data structure, which includes endurance levels associated with power-endurance modes. The manager module dynamically configures the apparatus to operate the memory arrays according to one of the power-endurance modes based on a desired endurance level.

Abstract: Fast verification of data integrity of non-volatile memory cells is disclosed. In one aspect, an estimate is made of a bit error rate (BER) associated with the data to be verified without fully decoding the data. If the estimated BER is below a threshold, then the storage system reports that the data meets a data integrity criterion. If the estimated BER is above the threshold, the storage system may decode the data to determine a BER and report whether the data meets the data integrity criterion based on the determined BER. The estimate of the BER may be based on a syndrome weight of the data, a BER of an XOR codeword formed from multiple codewords of the data, or a BER of a sample of the data. Hence, considerable time and power are saved verifying data integrity, at least when the data is not fully decoded.

Abstract: A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. In some cases, the recovered data may have a high bit error rate. To handle higher bit error rates, the use of soft bit data is incorporated into an encoded foggy-fine scheme.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives (SSDs). A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.

Abstract: A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.

Abstract: A storage system has a volatile memory, a non-volatile memory, and a controller. The controller of the storage system can implement various mechanisms for improving random read performance. These mechanisms include improved read prediction cache management, using a pattern length for read prediction, and a time-based enhancement for read prediction. Each of these mechanisms can be used alone on in combination with some or all of the other mechanisms.

Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.